Low Power Universal Gates for Approximate Computing

By Gaurav Goyal, Naman Gupta, and Rohit Goyal (Freescale Semiconductor India Pvt. Ltd.)

Abstract

Density and speed of IC’s have increased exponentially for several decades, following a trend described by Moore’s Law. While it is accepted that this exponential improvement trend will end, it is still not clear that exactly how dense and fast integrated circuits will get by the time this point is reached. Power has become a first-order concern for most designs, not only for the amount of functionality that can be placed on a chip, but also for the density and computing power of integrated circuits. Even though the energy consumed by a single CMOS logic gate to change state has fallen exponentially, the overall power consumption of the chip is still increasing. This paper talks about the power reduction technique with the help of a novel logic gate design.

I. INTRODUCTION AND RELATED WORK

Semiconductor technology has been continuously improved over the past two decades and has lead to ever smaller dimensions, higher packaging density, faster circuits, and lower power dissipation. Due to increased amount of functionality placed on a single chip, there is still a need to reduce the overall power consumption by the SoC so as to avoid the effect of high electric fields, to make the devices portable and also the overheating of the devices.

Earlier, the power consumption of CMOS devices was not the major concern while designing chips. Factors like speed and area dominated the design parameters. As the CMOS technology moved below sub-micron levels the power consumption per unit area of the chip has risen tremendously.

Approximate Computing is a technique which can perform calculations good enough for certain tasks that don’t require perfect accuracy, potentially doubling efficiency and reducing energy consumption. The human brain works in an interesting way! We are able to extrapolate information and fill-in the missing gaps. Hence perfect accuracy may not be a desired feature in many modern applications like media processing (audio, video, graphics, and image), recognition. This approximate or less-than-optimal result is a desirable trait if one can save power and/or area. In CMOS circuits, power dissipation occurs whenever there is a path for current flow formed between the supply and ground rails.

Fig. 1 Static and Dynamic power dissipation paths.

These paths are formed when the input to the gate of the CMOS circuits is applied and there is always a path present from the supply to the ground rails irrespective of the fact whether the input is static & changing. When the input is changing, in that case the power dissipated is known as the dynamic power of the design. When the input is static in that case the power dissipated is known as the leakage power.

As the VLSI industry is moving to the lower technology nodes, concerns on the leakage power dissipation has started to come in picture as leakage power is becoming comparable to the dynamic power of the design. In this paper, we propose the design of Low Power universal gates like NAND and NOR. The proposed gates have been designed in such a way that the paths formed between the supply and ground rails are less which results in less power consumption. The remainder of the paper is organized as follows. Section II discusses the implementation of universal basic building blocks: the NAND and the NOR Gates. Section III describes the simulation results for the leakage power and dynamic power of the proposed logic gates in comparison with the traditional static CMOS gates.

II. IMPLEMENTATION OF UNIVERSAL BASIC BUILDING BLOCKS

A. NAND Gate

The proposed NAND gate has been designed while keeping in view the minimum paths formation between the supplies to ground rails. Architecture has been designed in such a way so that there is minimum number of paths formed from supply to ground rails for different set of input conditions. At some places, input signals can be used in place of supply and ground nodes so that any path formed are not between the supply and ground rather than between signal and ground or supply and signal which reduces the power dissipation. Below is the Fig. 1 which depicts the basic static NAND gate which has been used extensively and is a conventional design from several decades.

Fig. 2 Basic Static NAND gate CMOS implementation.

In the above Fig.2, A and B are the inputs and Z is the output of the gate.

Here it can be seen that, there is always a path exists from the supply to ground and is a source of power dissipation for any combination of inputs. Fig. 3 depicts the proposed static NAND gate which can be used to provide low power solution. Here, the paths formed from the supply to ground rails are less with less power dissipation as compared to the conventional design showed in the Fig.2.

Fig. 3(a): Proposed NAND Gate for Approximate Computing

Fig. 3(b): Spice waveforms depicting proposed NAND

e.g. one supply node has been replaced with the signal ‘A’ which is not a path formed from supply to ground and hence no power dissipation for this MOS connected to input signal ‘A’. So, this way width of this particular MOS has been reduced considered to calculate the power dissipation and hence saves a lot of power.

B. NOR Gate

The proposed NOR gate has been designed while keeping in view the minimum paths formation between the supplies to ground rails. Architecture has been designed in such a way so that there is minimum number of paths formed from supply to ground rails for different set of input conditions. At some places, input signals can be used in place of supply and ground nodes so that any path formed are not between the supply and ground rather than between signal and ground or supply and signal which reduces the power dissipation. Below Fig. 4, depicting the basic static NOR gate which has been used extensively and is a conventional design from several decades.

Fig. 4 Basic Static NOR gate CMOS implementation.

In the above Fig.4, A and B are the inputs and Z is the output of the gate.

Here it can be seen that, there is always a path exists from the supply to ground and is a source of power dissipation for any combination of inputs. Fig. 5 depicts the proposed static NOR gate which can be used to provide low power solution. Here, the paths formed from the supply to ground rails are less or in a way with less number of MOS which in a way reducing the effective width of MOS for power dissipation as compared to the conventional design showed in the Fig.4. e.g. one ground node has been replaced with the signal ‘B’ which is not a path formed from supply to ground and hence no power dissipation for this MOS connected to input signal ‘A’. So, this way width of this particular MOS has been reduced considered to calculate the power dissipation and hence saves a lot of power.

Fig. 5 (a): Proposed NOR gate for Approximate Computing

Fig. 5 (b): Spice waveforms depicting proposed NOR

The proposed design of the Universal gates like NAND/NOR dissipate less power consumption when compared to [1]. The proposed design uses the output node to acquire the state ‘1’ with the help of NMOS network and ‘0’ with the help of PMOS network which would provide a drop of threshold voltage at the output node and could be taken care by tweaking the length of MOS or usage of level-restorer circuits can be used to have minimum power dissipation. Also, there are concerns if the signal transitions for the input signals are worse which can be taken care by keeping max transition fixed in the design.

III. SIMULATION RESULTS

Below table depicts the simulation results of leakage power.

Logic Function	Dynamic Power (W)	Leakage Power (W)
Static CMOS NAND	3.03 e-09	0.291 e-10
Proposed Approximate NAND	2.74 e-09	0.172 e-10
Static CMOS NOR	3.25 e-09	0.095 e-10
Proposed Approximate NOR	3.01 e-09	0.083 e-10

IV. CONCLUSION

The heat gradient across the chip can cause mechanical stress leading to early breakdown, worsening the reliability of the SoC and hence more and more attention will be focused on low power design techniques. Since, the proposed architecture of universal gates like NAND and NOR has been discussed which could be further taken as a base and other needed several other logic functionalities can be implemented.

REFERENCES

[1] CMOS circuits, “http://www.ece.mtu.edu/faculty/goel/EE-3130/CMOS-Circuits.pdf”

[2] Sill et al, “Low power gate-level design with mixed-Vth (MVT) techniques”, 17th Symposium on Integrated Circuits and Systems Design, pp-278-282, 2004.

Index Terms— Low Power Gates, CMOS Logic Gates, Low Power Computing, Approximate Computing, Leakage Power, Dynamic Power.