Vijeta Marwah and Saurabh Mishra, Freescale India
Embedded.com (August 31, 2014)
The intent of verifying a System on chip (SoC) is to ensure that the design is an accurate representation of the specification. Achieving fully verified SoC is an arduous task, yet verifying the SoC by using both directed verification and constrained random verification (CRV) can result in a 100% verified design.
Constraints help to reach coverage goals by shaping the random stimulus to push the design under test into interesting corner cases and avoid hitting invalid/illegal scenarios.
Using CRV, corner cases in the design can be exercised and system behavior under stress can be observed. Stress can be induced in the system by generating random traffic in the SoC. ‘Random traffic’ implies initiation of transactions from random selection of master to randomly selected slaves with any transaction type, size of data, and latency of transactions.
This paper describes how to use constrained random verification to uncover bugs that are difficult to find using traditional directed verification.
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