An innovative methodology to reduce routing capacitance of ADC channels

By Gurinder Singh Baghria, Sachin Kalra, Azeem Hasan, Naveen (Freescale Semiconductors India)

As the technology nodes are shrinking, achieving performance metrics for analog circuits are becoming more challenging. Moreover RLC parasitic and noise effects have hampered the performance of circuits on SoC, especially for the sensitive analog circuits like ADCs, Oscillators etc. With more and more complex designs with frequencies in Ghz range, noise sources have increased considerably which affects the intended behavior of the signal. This noise effect becomes more dangerous to the critical signals like ADC input channels where the performance specifications are very stringent. Traditionally there have been many methods to protect these critical signals from noise sources such as a high toggling net travelling alongside the critical signal. The effect of these noisy sources can be minimized by spacing the two signals apart or provide shield for these critical signals. Shielding the ADC channels will results in extra burden in terms of capacitance. Various forms of “C” (parallel plate cap, fringe cap) are formed in implementing shielding which increases the net delay of the signals and hence increase sampling time and decrease ENOB (effective number of bits). We are proposing an innovative approach which minimizes the extra parasitic resulting due to shielding of signals along with robust shielding for critical signals.

This Paper is lined up with the following details:

• Conventional Shielding approach and capacitance overheads due to shielding of signal
• Proposed approach for one critical net and its implementation.
• Proposed Shielding approach for multiple ADC channels.
• Capacitance (Parasitic) overhead comparison, conventional shielding v/s proposed approach.

Conventional Shielding method and capacitance overheads due to shielding of signal

Figure 1: Conventional approach

Conventional shielding approach for critical high speed ADC channels is shown in figure 1. CS is the critical signal that needs to be shielded from noise sources. Let’s assume the critical signal is in Mth metal layer, where M is one of the routing layers for metal. Conventional shielding approach have two lateral shield, on both side of critical signal used as a shield of CS which save it from noise aggressors in same metal layer (as shown the shielding nets of VSS in Mth layer in parallel to CS), along with that it has a metal plate of M+1 and M-1 metal layer on top and bottom side of the CS used as shield to avoid any coupling of noise from above/below layers. This is also called coaxial or tub shielding.

This ensures that the CS is not exposed to any external noise but the capacitance induced by the shield nets may still hinder the performance by degrading the critical signal, CS. If the total capacitance value exceeds the spec of the critical signal, the die designer opts to space apart the lateral shield nets to decrease the load of shield nets to CS and this will end up in wasting more channel space to route and hence the die area wastage. The SoC solutions integrate multiple ADC/DAC and other analog IP’s in design, resulting in multiple numbers of such critical channels and if this traditional approach is used for each such channels, this can result in huge die area overhead in terms of routing.

Total capacitance on the CS is derived with the following equation:

Proposed Approach

We are presenting a new approach of shielding the critical analog signals to reduce the noise effects and ensuring that the parasitic overhead is reduced so that the performance of critical signals is not compromised. Proposed approach overcomes the limitation of overloading the CS signal by shield along with maintaining the purpose of coaxial shielding of CS.

Key Features of the proposed approach:

• Reducing parasitic overheads: Purposed shielding methodology introduces a significantly less capacitance parasitic overheads as compared to conventional methods being used for shielding.
• Die area saving: Total C parasitic achieved is lesser as compared to conventional approach, so we can put shielded net closer to its Critical signal net, results in over all saving of die area in terms of routing resources.
• Noise Rejection: Purposed shielding approach provides a robust solution for noise rejection same as to conventional approach, which ensures the performance of critical analog signals.

Now lets explore this proposed approach in detail by taking example of ADC channel.

Proposed Shielding methodology for a single ADC channel:

Proposed approach act as a pseudo coaxial shield, which will work similar to coaxial shielding in terms of performance with reduced parasitic in terms of “C”.

Figure-2 show the proposed approach for shielding, similarly as in the conventional approach, CS (Critical signal) is routed in Mth metal layer have lateral shields of VSS in Mth layer on both side, but instead of complete metal plate in above and below layer, the top and bottom shield is only done over the lateral shields. This means we have only lateral shields running over the Mth metal shield in M+1 and M-1 layers also. As we don’t have any shield over the CS so the total load “C” on the CS is decreased and we have shield in top and bottom layer over lateral shield due to which the effect of any noise coupling from above metal layer and below metal layer get minimized. As top and bottom shield over lateral shields is of VSS (SoC ground), any noise due to M+2 and M-2 layer will be rejected.

The most critical part of the metal Zone over the CS in proposed approach in M+1 and M-1 layer is that this needs to be assigned as no routing and no tiling zone in M+1 and M-1 metal layers. This will ensure that there is no interference/noise induced by any signal routes or any unwanted cap effects by PG/metal fills at any stage of deign. So by this virtual shield, we are able to reject noise effects and also at the same time, reduce capacitive load on the critical signal.

With the proposed approach, C parasitic gets minimized with the purpose of coaxial shield intact. Total capacitance on the CS is derived with the following equation:

Figure 2: Proposed approach

Proposed Shielding approach for multiple ADC channels:

At SoC level, ADC channel gets routed in parallel to each other as shown in figure3a to avoid other net interference with ADC channels and to save die area by sharing shield nets between two channels.

Figure 3a Figure3b

In case of parallel channels like ADC, above and below shield nets in M+1 and M-1 to CS can be done to the outer most lateral shield as shown in figure3b, this further helps in achieving lesser “C” value and the effort of making shield nets at SoC and save cycle time for the ADC channel routing.

Comparison Results:

Capacitance overhead comparison of proposed approach v/s conventional shielding approach

Table 1 shows the comparison results between the proposed approach and conventional shielding approach.

1. R is resistance (Ohm) of ADC signal from pad to the boundary of ADC
2. C1 is the total capacitance of ADC signal using the conventional shielding method
3. C2 is the total capacitance of ADC signal using the proposed shielding method

Table 1: Conventional shielding v/s proposed shielding approach

Adopting proposed approach designer are able to achieve 28% lesser value for “C” (capacitance) as compare to conventional approach. In graph1 it shows that for every ADC channels with proposed approach the value of cap achieved is lesser.

ADC channels

Conclusion

Proposed approach of shielding reduces the routing capacitance of critical channels along with good noise rejection, save on die area and efforts in critical signal routing at SoC.

Authors

Gurinder Singh Baghria: Working at Freescale Semiconductors, India as Senior Design Engineer and has 4+years of experience in Physical Design activities.

Sachin Kalra: Working at Freescale Semiconductors, India as Senior Design Engineer and has rich experience in Physical Design, Analog Layout Design and Standard Cell Library

Azeem Hasan: Working at Freescale Semiconductors, India as Senior Design Engineer.

Naveen Kumar: Working at Freescale Semiconductors, India as Senior Design Engineer.