CPU Architects at the Brink: Where to Go Now?

By Ron Wilson, Editor-in-Chief, Altera Corporation

Pity the poor processor architect. Her job used to be so simple. Each new semiconductor process generation doubled the number of transistors per square millimeter, boosted the speed of circuits by a healthy fraction, and dropped the overall power. The architect’s golden rule was “Keep the architecture and tweak the implementation.” But things fall apart. Speed improvement and power reduction tapered off. You couldn’t just turn up the clock any more: architects had to use all those new transistors to exploit parallelism.

But where to find parallelism? First, we found the low-hanging fruit: instruction-level parallelism that we could exploit automatically with superscalar architectures. Then, with more transistors and pretty much all the instruction parallelism used up, we went after data parallelism with vector processors, and then after macro-level instruction parallelism—threads—with multithread and then multicore CPUs. For further reading: See a discussion of architectural issues in SoC FPGAs. Read an article on heterogeneous computing in data centers.

But suddenly we found ourselves staring into the slathering max of Dark Silicon. Power density from all those transistors was increasing so rapidly that we could no longer cool them if they all ran full-speed at the same time. We used clock gating, and then power gating, and finally outright reductions in transistor packing density to avoid melting the interconnect. But that limited our ability to throw transistors at the increasingly obscure opportunities for parallelism presented by the data and the algorithms. It looked like progress might be grinding to a halt.

So things stood at the beginning of this year’s Hot Chips conference. But in a triumph of determination over adversity, chip architects once again showed there was still room for innovation: places to find parallelism, ways to employ all those transistors, and techniques for keeping them cool.

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