SoC clock monitoring issues: Scenarios and root cause analysis

Geetika Arora , Neha Srivastava & Saloni Raina (Freescale Semiconductor)
EDN (December 18, 2014)

Clocking and Reset circuitry are the backbone of any SOC. With growing complexity of design, scaling of technology and introduction of multi core architecture, there has been an increase in demand of low power support, resulting in multiple clock and power domains. As this increases the level of complexity in the design, there are chances of introduction of clock domain crossing and reset domain crossing related challenges. As a result, greater are the chances of failures/defects, and any defect in this domain can prove catastrophic, especially when dealing with SOCs for the automotive industry.

To detect and tackle any such clocking failure, especially in security specific SOCs, a Clock Monitoring Unit is added to take corrective actions. But what happens if the introduction of this monitoring unit leads to some unexpected results when integrated in the SOC along with other clock/reset/fault correction modules. In this paper some of such scenarios where clock monitoring/recovery failed are presented along with the root cause analysis.

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