Sequential clock gating maximizes power savings at IP level

Ankur Krishna , chanpreet singh , Kshitij Bajaj , Ritesh Agrawal & Saurabh Shrimal (Freescale Semiconductor)
EDN (February 10, 2015)

Power Management is one of the major chip design challenges amongst all the dimensions of the design cycle. It poses problems for packaging, portability, & reliability (PPR), e.g.,“high system cost of fans – cooling, extending battery life & reduced electron migration” at later stage. Power saving and power dissipation calculation at a higher abstraction level than gate level becomes mandatory in this fast growing and restrictive time to market. Power explorations and its trade-off with area/timing becomes essential at the RTL abstraction level rather than waiting for this data after gate level runs. IP designers have a lot of flexibility to iterate to find ways to meet power budget at this point.

In this paper we talk about design exploration using the PowerPro tool. For analysis of power optimization based on this tool, we have included Advanced Driver Assistance System (ADAS) and cluster IPs with high speed processing requirements. These IPs have multiple complex operation requirements within a clock period, making them ideal candidates for power saving. The IPs under consideration are image processors, high-speed bus fabrics for a memory controller, display controllers, and video codecs.

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