Cheaper, Denser NAND Requires Better Error Correction

Stephen Bates, PMC-Sierra
EETimes (7/20/2015 02:30 PM EDT)

Solid-state drives (SSDs) have exploded in popularity as their prices dropped, driven by ever-diminishing NAND flash costs, but this less expensive and denser NAND flash requires better error correction codes (ECCs) in SSD controllers.

Traditionally, Bose-Chaudhuri-Hocquenghem (BCH) codes were used. They were more than adequate for large geometry NAND flash. However, cheaper and denser SSDs means BCH is no longer adequate and the search for alternatives has led most controller vendors to settle on low-density parity check (LDPC) codes.

There are several reasons why we are transitioning from BCH to LDPC, but they can all be boiled down to this: LDPC codes allow you to correct more errors for the same ratio of user data to ECC parity. The second part of this last sentence is really important. We don’t want to increase the number of ECC parity bits in SSDs because this leads to nasty things like write amplification (WA), format inefficiencies and increase costs.

So why didn’t we just use LDPC codes right from the start if they’re so good?

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