Reducing IC power consumption: Low-power design techniques

Sunil Deep maheshwari , Naveen Srivastava & Rohit Ranjan (Freescale Semiconductor)
EDN (September 24, 2015)

Designers always look for ways to reduce unwanted components of power consumption, either by architecting the design in a fashion which includes low power techniques, or by adopting a process which can reduce the consumption. However, some of these solutions come at the expense of performance, reliability, chip area, or several of these. Eventually, one has to reach a compromise between power, performance, and cost. The article below aims to discuss some of those techniques. These techniques are divided into Architectural Techniques and Process Based Techniques.

Architectural Power Reduction Techniques:

At the RTL level, one can take several steps to reduce the overall power consumption of the device. Typically, RTL based techniques minimize the dynamic power consumption of the device, however, using techniques like power gating, one can also reduce leakage power of a part of chip.

Click here to read more ...

E-mail This Article

Printer-Friendly Page