Hardware Acceleration for Embedded Computing

Ron Wilson, Altera
September 24, 2015

The Hot Chips conference for 2015 has come and gone, leaving us with a snapshot of some of the best contemporary thinking on silicon architectures. And while the scope of this year’s conference was wide—from wearables to supercomputers—a handful of papers, taken together, sketched out a strategy for the near future of embedded computing.

Why would we look to huge, ambitious chips to divine the direction of a market that loves microcontrollers? Two explanations come to mind. First is the growing virtualization of embedded systems. As more tasks migrate from dedicated hardware to the cloud, architects of server processors and the hardware accelerators that accompany them have to face the realities of the embedded systems world.

Second, embedded applications themselves are evolving. Growing use of machine vision and other robotic algorithms; of state estimators, Kalman filters, and similar techniques to augment direct measurements in feedback loops; use of computed executable system models in the loop; and exploration of machine-learning algorithms are all generating new, heavy-weight computing tasks in even familiar embedded applications. In many designs these tasks threaten to swamp the capabilities of even multicore embedded SoCs.

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