DFT – IP Reuse & SoC

by Jennic, Ltd.
www.jennic.com

To address the problem of SoC test Jennic Ltd have developed a proprietary IP test methodology founded on the concept of DfT ‘plug n play'. Achieving this is based on the adoption of an IP test interface protocol and the extension of the IP design conformance rules to include testability. A testable IP core can then be connected directly to the extensible ‘SCANBUS' test bus that is managed by a ‘SCANBUS' controller. Localised BIST controllers (memory and logic) can be engaged as well as the application of previously generated IP specific ATPG vectors.

Promoting the efficient reuse of internal IP and providing a stratagem for successful integration of 3 rd party IP has meant a tightening of the design process. Aiding this has been the adoption of company wide coding guidelines and the introduction of RTL purification tools. However, the embryonic nature of structured design for test methods for SoC design has meant that a custom methodology had to be developed.

A major barrier to achieving the productivity increases demanded by SoC design has been the failures of DfT techniques to address IP reuse issues. Integrated subsystems are now being specified as combinations of 3 rd party IP, internal IP, and custom designed blocks. In doing so design platforms are created which can address multiple products within the same application sphere. However, unless carefully considered testability can rapidly become the integration bottleneck.

The era of multi-million gate SoC design is now with us and the pace dictated by Moore's law continues unabated. Companies around the world are struggling to develop new design methodologies that seek to harness the power and flexibility these increased integration opportunities present. These must deliver ever more complex integrated sub-systems in timescales, that demand dramatic design productivity increases. In doing so the very paradigms on which current methodologies are based are being challenged. Design reuse, has and will continue to provide designers with many challenges. But unless test methodologies are also adopted that facilitate the efficient development of SoC test then the full potential of IP reuse will not be realised.