Strategy for reducing soft errors is needed

Strategy for reducing soft errors is needed
By Mark-Eric Jones, EEdesign
August 27, 2002 (1:45 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020827S0030

For system-on-chip designers, the trend toward increased, higher-density on-chip memory is unmistakable.

Already on par with logic and growing rapidly, memory today accounts for a greater proportion of system-on-chip die area than ever before. In fact, SoC memory has been growing steadily even without designers' explicit efforts to boost the proportion of memory in an SoC: Each new generation of process technologies shrinks features, providing more bits in the same area.

At the same time, traditional six-transistor (6T) memories show increased susceptibility to soft errors with each new generation of process technology. As a result, SoC manufacturers find themselves moving rapidly toward a reliability crisis.

To deal with the growing challenges of deploying large memory blocks in SoC devices, designers need to adopt new strategies that help reduce the occurrence of soft errors and the possibility of subsequent system failures.

According to the International Technology Roadmap for Semiconductors prepared by the Semiconductor Industry Association, 2002 represents a significant milestone in embedded memory.

This year, the proportion of memory on an SoC die crossed the 50 percent level. As a result, SoC designers' emphasis has changed in a subtle but significant way: Now they find that they have become designers of embedded memory rather than designers of embedded logic.

For all its importance in SoC design, however, memory reliability has received relatively little attention in the industry, despite clearly rising soft-error rates in conventional 6T memory.

In semiconductors, soft errors arise from alpha particles or cosmic rays, which create ionization paths through devices, resulting in functional failures. Measured in errors per megabit of memory, the soft-error rate (SER) is a measure of the rate of functional failures.

Fine-line geometries increase the likelihood of failures in dense designs such as DRAMs and SRAMs, in par ticular. In fact, for very deep-submicron processes, these phenomena even impact CMOS latches.

These soft-error effects have become even more pronounced with more advanced processes. In the move from 0.18-micron to 0.13-micron technologies, the 6T-SRAM SER-measured in failures in time (FITs) per megabit of memory-has risen from about 1,000 FITs/Mbit to 100,000.

What's more, the percentage of memory in SoC designs nearly doubled within the time frame of this process migration. With the combination of much higher SER and significantly more bits, SoC designs are left much more exposed to soft failures than earlier-generation devices.

Without corrective action, SoC devices face the possibility of dramatically higher failure rates due to soft-error phenomena. Using newer dynamic error-correction mechanisms, one-transistor (1T) SRAM cells offer both extremely high density and dramatically lower soft-error rates-below 10 FITs/Mbit for 0.13-micron devices running at speed.

At the same time, smaller o n-chip memory blocks do not require the high densities available with 1T cells. As a result, designers can use 6T memory cells for these smaller blocks, using logic design rules and more conservative cell designs to improve SER, reliability and yield.

For designers, skyrocketing soft-error rates stand as a growing barrier to successful deployment of memory-rich SoC devices with advanced process technologies. By matching memory architecture to specific need, designers who avoid one-size-fits-all strategies can meet the impending SoC reliability crisis without compromising critical design objectives for chip performance and die area.

Mark-Eric Jones is Vice President and General Manager, Intellectual Property, of Monolithic System Technology Inc. (Mosys), in Sunnyvale, Calif.