Custom Corner Characterization for Optimal ASIC/SoC Designs

Naveen Narang & Venkata Krishna, Open-Silicon
EETimes (5/25/2016 05:50 PM EDT)

Today's characterization tools offer a very good solution for extracting the best performance out of an ASIC/SoC for any specified PVT operating conditions.

A typical corner (TT) is no longer typical for most applications in today's world. For that matter, standard PVT Corners (FF/TT/SS), generally, do not represent the exact environmental conditions in which an ASIC/SoC will be functioning. This means the voltage may not be a nominal Vdd in a typical case or Vdd±10% in an extreme case; and the temperature may not be 25C in a typical case or 125C/-40C in extreme cases. Also, in today's market, every µW of power saved, and nS of delay avoided, makes a significant difference in a product's performance and cost. Therefore, it is important to know how a system behaves under real-time PVT conditions. One needs to characterize foundation IPs at these special (custom) corners to avoid overdesign and achieve optimal product for best power and performance.

When estimating the power and timing numbers of an IP at a custom corner (e.g., @95C and Vdd+3%), it is not easy to derive values from regular SS, TT, and FF characteristics as these may not support linear extrapolations. Even small errors in calculation can be very risky. One approach is to use characterization tools (e.g., Silicon Smart from Synopsys) that can easily characterize foundation IPs to estimate power and performance of an SoC at any custom corner with substantial accuracy using reference ".lib" files.

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