Easing Heterogeneous Cache Coherent SoC Design using Arteris' Ncore Interconnect

By Loyd Case, Senior Analyst, The Linley Group

Heterogeneous processing has become a hallmark of mobile SoCs, but designing cache coherency across these diverse processing elements can be difficult. Standard on-chip interfaces and network-on-a-chip (NoC) technology are the first step, giving architects IP to efficiently connect compute processing elements as different as CPUs, GPUs, and DSPs. Hardware IP to enable coherent communication between different types of compute engines is the next step. This white paper describes how Arteris’ Ncore IP can help architects design processors fully supporting coherency between heterogeneous elements. The Linley Group prepared this paper, which Arteris sponsored, but the opinions and analysis are those of the author.

SoC complexity increases every year. The quad-core processors of a few years ago have evolved into monsters employing ten CPU cores plus additional heterogeneous processing elements. Rather than being isolated into application-specific silos, GPUs, DSPs and ISPs have been promoted to peers with CPUs within the SoC, contributing heavily to the overall workload processing.

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