Hitless I/O: Overcoming challenges in high availability systems

Shyam Chandra, Lattice Semiconductor
embedded.com (October 11, 2016)

High availability systems such as servers, communication gateways and base stations need to be continuously operational. Once installed in the field, software upgrades handle feature enhancements and bug fixes. As a result, these systems are designed in such a way that their functionality can be updated without interrupting its normal operation. Programmable Logic Devices (PLDs) are commonly required to support in-system design updates. The improved design convenience and excellent performance at a lower cost make PLDs ideal as board hardware management devices in these systems, where they manage on-board DC-DC converters, monitor and control critical signals, aggregate serial communications, and perform other housekeeping functions.

The Indispensable PLD

A PLD consists of a number of programmable function units. These units are configured and interconnected to implement board specific hardware management functions. Typically, a software design tool converts a given logic function, such as a board hardware management, into a PLD-specific configuration bit stream, which configures the program function units and interconnects them. The configuration bit stream is stored within a PLD’s on-chip configuration Flash memory. When the board is powered on, the contents in the configuration Flash memory are automatically transferred to its on-chip configuration SRAM, which in turn configures the programmable function units to perform the desired hardware management task. To update the hardware management functionality, a different bit stream is loaded into the configuration Flash memory, in background, at any time without interrupting hardware management functions performed by the PLD. To transfer the newly stored Flash memory configuration Flash onto the on-chip SRAM the board is power cycled, interrupting the system normal operation (Fig.1).

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