Commentary: Canadian universities tackle SoCs

<B>Commentary:</B> Canadian universities tackle SoCs

Commentary: Canadian universities tackle SoCs
By Peter Stokes,
October 11, 2002 (5:02 p.m. EST)
URL: http://www.eetimes.com/story/OEG20021011S0042

It's no secret that many of today's sophisticated CAD tool algorithms, novel circuit designs and advanced methodologies originate in university research laboratories. Across Canada, many bright minds are working on problems barely visible on the five- to 10-year horizon in microsystems development.

For researchers, the university environment is ideal for scientific exploration and discovery. The innovative solutions being developed in university labs will bring microsystems design methodologies into lockstep with manufacturing advances, enabling hundreds of millions of transistors to be placed on a single CMOS substrate.

In Canada, more than 30 universities have teamed up to tackle system-on-chip (SoC) challenges head-on. With the help of industry and government investment, and strategic leadership by the Canadian Microelectronics Corp., a national System-On-Chip project valued at over $30 million is entering its second year. Students and profes sors are engaging in projects that deal with design reuse, soft intellectual-property (IP) block authoring flows, derivative design and SoC platforms. Such work is leading to the building of a university design environment that may become the envy of academic communities around the world.

After careful consideration, an initial SoC platform targeting Bluetooth wireless apps was chosen as the vehicle for enabling a variety of research opportunities in applications, methodology and algorithms. The platform includes analog/mixed-signal components and focuses on power efficiency typical of portable electronic products.

The SoC platform includes an ARM embedded processor, Amba bus, Virage embedded memory and Tality Bluetooth cores. Rounding out this collection of intellectual property is a Mentor real-time operating system, Tality Bluetooth protocol stack and Ethernet MAC.

The design flow basics include Cadence's VCC for making architectural decisions, Mentor's Seamless to assist with hardware/softw are co-design and Synopsys and Cadence tools for synthesis and physical design, respectively. An ARM rapid-prototyping board consisting of Xilinx gates and an ARM processor accelerates verification and IP validation. Embedded software tool chains from ARM and Mentor interface with the platform application programming interface. An IP management capability is being assembled, based on Synchronicity's tools.

Isolated and protected research labs are tied together in a secure fashion by using firewall and encryption technology. Experimental tools and techniques are being devised to create virtual collaborative design teams that draw together individuals from different locations.

What does this mean for university research? It means an entirely new level of design sophistication and the opportunity to tackle some new and challenging issues. With pre-designed and verified platforms, researchers can focus on specific research problems without having to design the entire chip. Some of these include:

New SoC-scale design-for-test techniques;

Block-to-block communication synthesis;

Noise and power issues related to integration of digital and analog circuitry;

Hardware (custom logic)/software (embedded processor) cost analysis;

The impact of architectural decisions on performance and power consumption;

IP block-authoring methodologies that encourage IP reuse; and

Verification methodology of complex, hierarchically deep designs.

The longer-term vision for the System-on-Chip Research Network assumes relatively effortless SoC design to allow more sophistication. With the planned availability of embedded processors, a variety of memory architectures, embedded software flows and a library of specialized IP and methods, the "next big things" can be explored.

Future projects might include the addition of microelectromechanical systems-based sensors and actuators on an SoC accompanied by high-speed optoelectronic interfaces and hundreds of millions of transistors.

Peter Stok es has more than 15 years of experience in supporting university research. He works at Canadian Microelectronics Corp. (Kingston, Ontario).