Assertions aid design-for-verification strategy

Assertions aid design-for-verification strategy
By Richard Ho, EEdesign
October 18, 2002 (2:57 p.m. EST)
URL: http://www.eetimes.com/story/OEG20021018S0032

In past economic slowdowns, semiconductor companies that continued to innovate emerged with dominant positions in new and expanding markets. At first glance, innovation is associated with feature advancements, such as support for emerging communication standards or new architectures. But innovation also means being the first to market.

Arguably, functional verification poses the greatest risk facing design teams trying to meet tapeout schedules. Design teams working on the largest ICs report that more than two-thirds of their time and resources are spent on functional verification. In the same way that design-for-test and design-for-synthesis overcame respective bottlenecks in automated test pattern generation and register-transfer-level synthesis, what is required now is a design-for-verification methodology, where a small investment from designers reaps large benefits when verifying designs.

Assertion-based verification (ABV) is an evolutiona ry change to current practices that delivers a design-for-verification methodology. They are simple statements of design intent, or assumptions made during implementation, instrumented in RTL code at the same time that design coding is done. They represent combinational or sequential conditions that must be true at all times in the circuit.

In general, assertions are specified to declare design intent, to declare design assumptions or to declare interface assumptions. ABV combines assertions, simulation and formal techniques to verify from the block level through to the chip and system levels, effectively automating verification. The benefit of simulating with assertions is better and smarter observability of the design internals. Debugging is greatly simplified, since problems are flagged with exact locations and times by assertions.

With formal verification, billions to trillions of input sequences can be examined rapidly, looking for bugs in corner cases. No advance in simulation technology will b e able to match the power of formal verification.

Further, ABV provides a seamless methodology: The designer places assertions once, and they are leveraged many times. ABV is design-for-verification. The number of bugs found corresponds to the number of meaningful assertions specified.

In design-for-verification, designers specify the assertions as they are coding the design, allowing assertions to be instrumented without additional investment in time. For this investment, the designer reaps several benefits: self-documenting code, defensive design practice, the ability to specify verification targets and the ability to apply formal verification at the block level. The benefits extend through the design cycle, simplifying the verification task and providing more thorough verification at the chip and system levels.

In an industry of survival of the fittest, functional verification may be the factor that determines which companies dominate. And design-for-verification and ABV improve the efficienc y and effectiveness of functional verification.

Richard Ho is senior architect and co-founder at 0-In Design Automation.