Leveraging UVM based UFS Test Suite approach for Accelerated Functional Verification of JEDEC UFS IP

ShengHung Yen (Spreadtrum), Vishnuvardhan Reddy Mandala (Synopsys)

ABSTRACT

Reduction in time to market is one of the main aims of IP Vendors with precise testing of IPs. With the continuous increment in complexity of mobile systems, functional verification became most challenging part of chip design. To reduce time to market, IPs needed for SOC must be developed in parallel to top level design and should be verified in parallel. Test suites are powerful entities with complete set of package that will have the intended tests to check the compliance of the IP with that of the specification and vendor’s can identify more bugs in IPs within a given period. Coverage is another added benefit with the Test suite and it is an essential check to be done for the IPs to measure the verified portion of IP functionality. IPs can have several types of interfaces based on performance, configurability, cost etc. UFS Test suite provides a good solution to test for these types of requirements with various types of interfaces (APB, AXI, OCP) supported.

1. Introduction

With the rapid development of modern mobile systems there is a great increase in the complexity involved in the IP and SOC designs and correspondingly the functional verification also becomes a challenge. To reduce time to market, IPs needed for the SOC must be developed in parallel to the top level design and should be verified in parallel. This requires strong methodology and infrastructure support which allows the SOC design team to be aligned on the requirements with IP teams. Methodology should also ensure that SOC design team gets the required data for the IP to proceed with the complexity of SOC design.

1.1 What is a Testsuite and Why one should use UFS testsuite?

Testsuite is a collection of pre-build tests and coverage model which can help the users to check the compliance of an IP with specification. Test suites will provide a better solution for functional verification of these individual IPs and the vendor can test the IPs and can identify more bugs in them. This paper starts with highlighting what should be the framework of a scalable JEDEC UFS testsuite architecture with an underlying Verification IP or a BFM. It then talks about how we leveraged the Test suite to verify the JEDEC UFS Host Controller which is an IP in our sub-system design and how the test suite helped to achieve the objectives of verification such as DUT bugs, coverage, protocol compliance etc.

The paper describes the following points considering UFS Host Controller IP as the DUT:

• Sequence driven functional verification: Sequence driven and debug approach which is developed and successfully implemented using UVM and the benefits of the same to enable parallel verification of UFS IP and which can be used into the SOC designs.
• Bus Interface Integration ease: Integration eases with support for generic application (BFM that can support multiple types of interfaces (APB, AXI etc.).
• Abstraction through Sequence Wrapper: Inbuilt conversion of abstract level sequences to JEDEC UFS HCI read/write sequences.
• Customized DUT Resister read/write: Scope for customized register read/write for programming DUT registers as per the user requirement.
• Coverage: Functional coverage and metrics to measure it to get a quick closure of functional coverage with the provided rich set of test cases including CTS tests and some complex test cases.

2. Verification of UFS Host Controller

UFS is a Low power and high performance next generation Flash Storage and data transfer technology for intelligent mobile phones and tablets with high data transfer rate. UFS Host controller is based on JEDEC UFS standard that can be operated with MIPI UniPro and MPHY as the underlying layers. In this project UFS Host Controller uses AMBA APB for DUT register programming and AMBA AXI for DUT Memory programming, however UFS Test Suite is configurable to support multiple Bus Protocol interfaces. In this paper UFS Device refer to the UFS Device Verification IP that we used and the UFS Host refer to SPREADTRUM UFS Host DUT.

UFS Host controller initiates stimulus and will receive the response from UFS device and act based on the received response. UFS Host works based on the UFS Host controller interface(UFSHCI) that contain a register set which application software makes use of for initiating the stimulus.

2.1 UFS Host Controller verification environment in a testsuite framework

Fig 1 is the block diagram highlighting the logical representation of UFS VIPs connected with the UFS DUT. The data flow is based on the UFS HCI register programming. Once the data is available with the application software, it will program the HCI registers and will select an empty slot (32 slots will be available for data and 8 for Task management as per UFSHCI 2.1). Once the empty slot is found then Application software will set the Doorbell register and based on Doorbell register, UFS Host will pich the data from HCI registers and will frame the UPIU and will transmit the UPIU.

Here the Sequence wrapper and UFS DEVICE VIP are connected at DUT’s application side and PHY interface. At the PHY interface the UFS VIP is connected to DUT with RMMI/SERIAL interface as UFS DEVICE VIP. The Sequence Wrapper converts the UFS sequences to APB/AXI transactions.

Figure 1: UFS Host Test Suite Architecture diagram for SERIAL/RMMI Interface

CPort is a communication channel between the Application layer(UFS) and the underlying layer(UniPro). If the intent of the verification is to test UFS features alone and not UniPro related features, then to speed up the simulation, CPORT level connection topology is also provided for the UFS Host Test suite and this will help to validate the UFS level features in quick time Suite where the UFS DUT can directly communicate with the UFS DEVICE VIP through CPORT interface. With CPORT back to back topology all the delays involved in link layer(L2) and the PHY layer will be eliminated and the simulation speed is improved by large extent.

Figure 2: UFS Host Test Suite Architecture diagram for CPORT Interface

Provision is given for CPORT topology to communicate with required bit width of the interface, also asynchronous TX and RX bit width is also supported by VIP.

UFS Host in this case is DUT and it requires a UFS Device which can respond to the commands sent by the UFS Host and the UFS Device should be able to send all sort of the possible responses (positive scenarios as well as negative scenarios) for the testing of DUT. UFS Device should interact with the memory for data storage/retrieve as per the received commands from UFS Host.

2.2 Sequence wrapper

Sequence wrapper is used to convert the user level sequences to the corresponding address and data transactions that can be sent as inputs to the DUT through AMBA AXI/APB interfaces. Thus, the converted sequences will have the REG/MEM READ/WRITE type of transaction created for the DUT. In this case User level sequences contain UPIU transactions and these UPIU transactions are converted to AMBA transactions, which will be used for the register/Memory programming of DUT, in this way user can provide the stimulus at transaction level and test suite will take care of the Register programming.

Transaction flow of the user level sequences is as shown in below figure

Figure 3: Transaction flow diagram highlighting sequence level to DUT register programming

2.3 Customized DUT Resister read/write

A dedicated port is provided to the user for programming the DUT specific registers as per specific requirement such as

1. Scaling down of the internal DUT timers (Reducing the DUT timers feature can be used to reduce the timers present at the DUT so that the overall simulation time can be reduced)
2. Operate the DUT in some specific configurations through required Register programming that are not mentioned in the specification (for example low power mode etc.).

An extensive set of sequence collection is provided to reuse the sequences for generating any required scenario. User can readily reuse the given set of sequences and the Sequence wrapper can readily be used to convert these new sequences to the AMBA REG/MEM read or write transactions.

3. Test Suite Operating Modes

Each test case provided in the UFS Test Suite can be run in two modes

1. VIP-VIP mode
2. VIP-DUT mode

3.1 VIP-VIP mode

In VIP-VIP mode, the UFS Host will be a UFS Host VIP and UFS Device will be UFS Device VIP and this mode is provided to the user as a reference for testing the scenario or to have a look and feel of the scenario. This mode can be used as an example and when a user faces any issue with any of the test case, and then this mode can check the behavior of the VIP for such ambiguous scenarios.

3.2 VIP-DUT mode

In VIP-DUT mode, UFS Host will be UFS Host DUT and the UFS Device will be UFS Device VIP and this is the mode in which users can test out their DUT and the real time traffic will be generated by the DUT and the UFS Device VIP will be responding to the inputs from the UFS Host DUT.

3.3 Compliance Test Suite Support

All the compliance tests that are part of the JESD224 CTS (compliance Test Suite) are covered as part of UFS Host Test Suite and in addition to these, scenarios that are considered as complex to check from design perspective are also added in the Test Suite. Some tests may not be applicable for all the topologies (SERIAL, RMMI, CPORT), such as the tests involves physical layer procedures and DME operations are not applicable in CPORT mode and for these tests pre-termination will be given at the build_phase of the UVM Test flow with a planned early exit so that they are not shown as Test failure in the regressions. For example, in CPORT back to back testing, DME_RESET and Linkstartup are not applicable, so for this type of test planned early exit will be provided in the CPORT mode.

3.4 Scoreboard

Score boarding is done from Host to device as well as Device to Host side to ensure the Data integrity on both sides. Score boarding will also ensure in-order transaction flow. Synopsys UFS Host Test suite facilitates user to connect the scoreboard i.e. on the host side scoreboard can be connected to the VIP Sequence wrapper part sitting above the Application layer side of UFS Host DUT and on the UFS device side, scoreboard can be connected to the Synopsys Device VIP monitor. UFS Testsuite also provides a Readymade scoreboard which can be used directly for validating the UCFS Level traffic and it can be turned off for error injection scenarios.

3.5 Coverage

Coverage model is measured based on the transmitted/received traffic at the UFS Device side such as the traffic in both Transmit as well Receive directions. Receive direction traffic is nothing but the traffic that was sent by the UFS Host. So the traffic that was sent from the UFS Host is same as the data traffic that was received at the UFS Device. So analyzing the data traffic at Device is same as getting the coverage metrics of the UFS Host in this case. In addition to the UFS layer coverage, UFS HCI level coverage also implemented to get a closure on scenarios and register set exercised.

4. Results

With the usage of the above mentioned UFS Test Suite, the time to test the DUT was considerably reduced by a larger amount and the requirement of writing new test cases to test out the individual UFS Host Controller IP was reduced for the design engineers and they could focus more towards fixing the DUT issues and simultaneously to integrate the IP to the full system development. The Test Suite is developed such that it is a readymade product and which can be used readily by installing and start running the test with minor modifications in specifying the compilation order of the DUT files.

These were some metrics/results that we observed.

• Time to bring-up test bench environment with the UFS Host controller: 1-2 days to get integration done
• Time to reach coverage goals (99% functional coverage): 2 weeks
• UFS Host Controller test-suite with the below additional features:
  • Additional mode(VIP-VIP) of executing the test case so that user can have reference of the scenario when facing an issue in running the test with DUT.
  • All the CTS test cases of the standard JESD224 are provided.
  • Added additional complex tests apart from CTS tests in UFS HCI test-suite.
  • Creation of a register abstraction layer which enables ease of programming over the APB interface on the Host side.
  • Additional updates to Sequence wrapper for DUT registers/Memory programming so that user can have flexibility in his design.
• Number of test cases and issues found
  • 360 tests, >40 DUT bugs found

5. Conclusion

For reducing the time to market of the today’s complex SOC designs, state of the art verification is compulsory to achieve a bug free design. Prior to the test suites there are Verification IPs which can be used to verify the DUT, with the overhead that the entire environment and the test cases and the entire frame work should be developed by the DUT designers itself and this entire process may eat up lot of time of the DUT design and verification engineers.

Keeping all these requirements into consideration a scalable, configurable, and easy to integrate solution is required for the verification of the DUT at IP Level and Synopsys UFS Host Controller testsuite is a perfect example for such a solution which is used at SPREADTRUM to meet the verification requirements and to identify and address the complex issues in the UFS Host Controller DUT. As the Test suite is developed using the advanced UVM infrastructure, the integration part of this DUT into the verification environment is done seamless because of the wee defined UVM approach.

While selecting commercial Verification solution to verify these complex protocol IPs, the following criterion were laid down:

• Availability of UVM based VIPs which will have the integration ease with advanced methodology support and roadmap to support future versions.
• Availability of test-suites that can reduce the job of the DUT verification engineers to write new tests and develop the verification environment from scratch.
• Availability of scoreboards to ensure data integrity and validate the behavior of the DUT
• Ability to program the register interface of the DUT, with user defined custom bus protocol.
• Verification vendor should be able to provide the required scenarios to test the VIP and to have any specific requirements in the test suite which are considered as critical from DUT verification engineer point of view.

6. References

[1] JEDEC UFS 2.0 specification (JESD220B)

[2] JEDEC UFS CTS (JESD224)

[3] JEDEC UFS HCI (JESD223B)

[4] MIPI UniPro 1.61 specification

[5] MIPI MPHY 3.0 specification

[6] VC VIP MIPI UFS Test Suite User Guide

[7] VC VIP MIPI UniPro VIP User Guide

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