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Improve FPGA project management/test by eschewing the IDEIlia Kalistru, Infotecs JSC 1 Introduction A common way to do an FPGA design is to create a project using your design tool. A project consists of a hierarchy of directories and many files. Creating a project, you have a nice GUI, wizards, and you can even create your design without touching your keyboard – with mouse clicks only. It works well for small and simple projects, or projects where you only combine existing IPs in a purpose-specific mixture. Unfortunately, in larger projects – with tons of code – this project-centered approach creates significant problems, such as with attempts to use source code control systems (SCCS), test-driven development techniques, or any other systematic testing methodology. Using design tools in non-project mode eliminates these problems.
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