A Brief History of Process Node Evolution

Priyank Shukla, Director, Analog Mixed Signal Design, Insilicorp

The semiconductor industry has produced improved Integrated circuits (ICs) year after year by reducing chip area and making ICs more power efficient. In addition to new circuit innovations, a major driver for these improvements has been the advancement of fabrication process or technology nodes that essentially make electronic devices smaller and more power optimized. The evolution of fabrication process provides these improvements, also known as “scaling” trends, without requiring any new circuit/architectural innovation. Major semiconductor companies make elaborate roadmaps to improve IC performance by exploiting process advancement as well as design innovation. Most notable of these companies is Intel, which came up with “tick-tock” model, where a "tick" means area and power improvements through shrinking of the process technology and a "tock" introduces improvement through a new architecture.

The need for a well-aligned roadmap for process improvement has been felt since the early days of the semiconductor industry. As the evolution of process nodes is not driven by a single driver and the complete semiconductor ecosystem is not controlled by a company or entity, it is very difficult to align on such a roadmap that assigns fix dates for the development of process nodes. Since its inception in 1992, Semiconductor Industry Association (SIA) has provided National Technology Roadmap for Semiconductors (NTRS) which are technology roadmaps trying to show the “targets” that need to be met by “technology solutions” under development. In 1998, the SIA with cooperation with worldwide industry participants created first global roadmap: The International Technology Roadmap for Semiconductors (ITRS) and since then The ITRS has laid out the foundations of the era of “scaling”. The first phase of this era is characterized by geometrical or constant field scaling where horizontal and vertical physical feature sizes shrunk to improve density.

The figure below provides the intuition for scaling -

As shown in the picture, a 30% reduction in the dimensions of the rectangle reduces the area by 50%. This means a scaling factor 0.7x ( =0.7) is needed to reduce area to half.

Reduction in the size of the devices reduces effective capacitance, which in turn reduces device delay by 30% (0.7x), making devices run faster. One measure of the fastness of the devices in a process node is operating frequency, which is defined by frequency of ring oscillator as shown in the below fig

If the delay of each inverter of the ring oscillator is , the topology of the circuit ensures that the input of the first transistor gets fed back after 3 , making the frequency of this oscillator . So, 30% reduction in delay (0.7x ) will correspond to 40% increase in operating frequency – clear advantage of scaling!

Finally, to keep electric field constant, the voltage in a process is reduced by 30%. This way, each new technology generation doubles transistor density while keeping power consumption the same.

This scaling factor of 0.7x provides intuition for process nodes roadmap from 180nm to 180*0.7=130nm to 130*0.7=90nm to 90*0.7=65nm to 45nm, 32nm, 22nm, 16nm and so on. This seems simple in terms of the numbers – but what do these numbers represent? A simple answer – feature size!

Before 32 nm node, the process node roughly corresponded to the minimum value of drawn gate length. And it could be said that the feature size is an indication of the gate length. It is important to highlight here that the actual channel length or effective channel length of the implemented transistor would have been lower than node value considering overlap from source and drain regions on gate area and thereby reducing channel length. As a matter of fact, the effective channel length remained constant from 90nm to 32nm.

What else can be done to pack more transistors in per unit area? Traditionally, microprocessor unit (MPU) products have driven the reduction of gate length While DRAM used to drive the lithography half-pitch. Most of the ASICs and SoCs employ MPUs and their area is dominated by digital circuits that are synthesized using standard cells and the height and width of standard cells are multiple of Contacted Gate Pitch and Minimum Metal Pitch as shown below

For 32nm process, different foundries had the value of these pitches around 110-130 nm. If a foundry can fit a complete MOSFET device i.e. source, channel and drain in one gate pitch, the absolute value of gate length would not matter and the area of the digital IC will scale with the product of metal pitch and gate pitch. So, to reduce area further, it makes sense to reduce the pitches. By scaling metal and gate pitches, foundries can continue to offer process improvements without reducing effective channel length. And with this approach, the correlation of gate length and node name became dilute. In the 2009 ITRS, the references to the term ‘technology node’ were eliminated. Also, roughly after this time, the process nodes scaled in a way that could be described as equivalent scaling in which the three-dimensional device structure was improved or scaled to improve performance. As far as the names of latest process nodes such as 14/10/7 are concerned– they are simply a commercial name for a generation process technology, with no relation to gate length, metal pitch or gate pitch.

What is the way forward for the roadmaps? With the generally acknowledged sunsetting of conventional Moore's Law, where scaling is achieved merely by process improvement, ITRS issued its final roadmap in 2016. A more generalized roadmapping considering other possible ways to further provide scaling advantages, IEEE's initiated Rebooting Computing and planned the International Roadmap for Devices and Systems (IRDS). As of today, ITRS is no longer being updated and IDRS is its widely accepted successor.

The discussion on the evolution of process technology cannot be complete without discussing developments in photolithography. State-of-the-art fabrication process uses 193 nm ultraviolet argon fluoride laser for photolithography. To create a feature size that is an order of magnitude smaller than the wavelength of light used, a class of technologies known as Multiple patterning (or multi-patterning) is employed. These techniques introduce new design rules that make layout increasingly difficult. To overcome these challenges, industry’s official hope is EUV – Extreme ultraviolet lithography which is the next-generation lithography technology that employs an extreme ultraviolet (EUV) wavelength, currently expected to be 13.5 nm and is planned for high volume use by 2020.

While system-level improvements are being discussed currently to continue scaling. The industry is still working hard to reduce feature length of a process with use of newer techniques.

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