Gate-array-like processes gain ground

Gate-array-like processes gain ground
By Ron Wilson, EE Times
December 6, 2002 (3:09 p.m. EST)
URL: http://www.eetimes.com/story/OEG20021206S0034

SAN MATEO, Calif. - Growing pressures are raising the profile of metal-mask programmed logic arrays for system-on-chip (SoC) implementations, which in turn has already produced a resurgence in such product lines. Now a study from eASIC Corp. suggests that using only vias to program the logic array could enable direct-to-wafer e-beam technology, eliminating several mask steps and easing a number of important constraints on gate array-like processes.

In metal-mask programmed technologies, the hard work of chip fabrication-the critical diffusion masks, poly mask and first couple of metal masks-is done ahead of time in a design-independent fashion. That creates a base layer of logic cells, which can be wired together by the final metal mask layers to implement a particular design. The underlying wafers originally were fabricated as arrays or, later, as sea-of-transistor pairs. Today, the underlying structure tends to be a more FPGA-like array of complex logic cells. But the idea of metal-mask characterization remains.

Indeed, some ASIC vendors, including AMI Semiconductor, Chip Express and NEC Microelectronics, have introduced such products.

Designer's dream

The concept has obvious appeal to the design team. The complexities of full-on chip design are the responsibility of the ASIC vendor, as is much of the nonrecurring engineering. The design team need only develop a netlist to translate into metal masks and then pay for the masks, the ASIC vendor's services and whatever wafers it has actually finished.

The idea also has interesting implications for foundries, some of which are important for design teams as well.

On the plus side, the higher-level metal masks are about the least critical in the entire process. They contain no subwavelength features, so they do not require phase shifting or optical proximity correction. In fact they frequently don't even require current-generation steppers: They can be exposed on older equipment. And while the metal stack processing in a copper-damascene process is never trivial, it is at its easiest in the coarse-pitched upper metal layers. Both unanticipated process results and defects are less likely to be a problem.

On the minus side are a few interesting questions. Howard Sachs, president of Telairity Semiconductor Inc. (Santa Clara, Calif.), pointed out that there's not a lot of experience around the industry in warehousing partially completed copper-damascene wafers. That situation becomes even more of an issue when the industry starts to move toward the highly absorptive and fragile low-k dielectric materials in the metal stack. Shelf life and even the nature of contamination risks are not well known.

Also, while producing metal masks for a 130-nanometer or lower process is easier than, say, the poly masks, it is not trivial. Lots of features still must be written and inspected, critical alignment still matters if you are trying to maintain an aggressive fully contacted metal pitch, and via masks remain an issue.

That latter point caught the attention of Zvi Or-Bach, president and CEO of eASIC (San Jose, Calif.). Or-Bach noted that most modern logic-cell based ASICs are designed so that they can be configured using several metal layers, with associated via layers. With perhaps a slight reduction in generality, Or-Bach surmised, it would be possible to design a logic module array structure in which the interconnect segments were fixed, and all the configuration was done with the via masks.

At first glance, that may not appear to be a big gain. Such a design would mean that some of the upper-layer metal masks would be done by the ASIC vendor ahead of time, saving a bit of time and money. Maybe not such a big deal.

But, Or-Bach pointed out, if you are writing a via mask, you are writing only a tiny fraction of the total reticule area. Therefore, an e-beam system can write the mask much faster than the time it would require for a metal mask.

In fact, Or-Bach's calculations i ndicate that the writing time is so small that the mask step could be skipped altogether, and the vias could be formed economically by direct-to-wafer e-beam writing, one wafer at a time.

That raises a whole new set of possibilities for streamlining the production process for metal-programmed ASICs, potentially making feasible both very fast turnaround and very small minimum lots.