How to apply SERDES performance to your design

As these requirements evolve, technology evolves, likewise the designers must stay current with new technologies. Serializers and deserializers are an emerging technology that allows designers to cross some of the former bandwidth bridges that existed with previous technologies. As with all new interface technologies, SERDES has a slight learning curve.

Any application having requirements for wide widths of data that needs minimal skew between outputs and between devices is a prime candidate for SERDES technology. The 10:1 devices (1023/1224) offered by various vendors have enough drive to allow a small multi-drop or multi-point configuration.

A common configuration for devices with Low Voltage Differential Switching (LVDS) outputs is a simple point-to-point type over a pc board or cable. The 10:1 devices can use an output termination resistor sized down to 27W, which is required when several devices are coupled onto a single parallel path, i.e. multi-drop. The current direction for the backplane market is a point-to-point topology with a master switch. SERDES is easily applied to this environment due to the minimal wires that must run through the switch. Redundancy is also an available advantage for a switch interface.

SERDES technology is composed of a dedicated serializer / deserializer pair. A custom serialized output is the result of stringent timing components and reproducible signal positioning. On typical inputs, TTL signals (0V to 3.3V swing) enter the serializer "horizontally" and are then "vertically" aligned such that in one clock period, one set of parallel bits, or just one word, is transmitted. The internal frequency of the serializer must be faster than the incoming TTL data.

The frequency of this internal clock is set by the compression / decompression factor of the device pair and phase lock loop timing. One would expect a 10:1 serializer to simply have an internal frequency of 10 times the TTL frequency. However, this is not always the case. The 10:1 SERDES pair that is currently on the market began as a custom pair that required the two devices to only be connected by a single data pair. How does the clock get shared between the two devices?

The 10:1 family uses an embedded clock to synchronize the serializer and deserializer. This embedded clock is made up o f a start bit, always high, and stop bit, always low. The placement of these two bits is crucial to the low skew operation of the device. Between these bits are ten distinct data bits, making the total length of one serialized signal actually12 bits. When looking at the entire sequence, it is difficult to see exactly where the oscilloscope is triggered in the data pattern. For this reason, it is common to insert a known data pattern, K 28.5 or similar, when trouble shooting.

With several vendors offering SERDES devices, and most of the devices being very similar, it is important to understand datasheet specifications. Comparing two "similar" specifications, jitter for example, can appear to be clear while a minor adjustment in one vendor's testing methodology discredits any comparison between the two specifications.

It is therefore important to not only understand the specification itself but also be familiar with the way in which the characterization data was collected. If a question aris es on a specific SERDES device, do not hesitate to call the vendor. Not only is it common for vendor's application engineers to communicate with a specific designer on a design win, it is expected.

When differential signals reach speeds over several hundred MHz, eye opening measurements are needed to evaluate signal integrity. These measurements are often summarized as jitter. Jitter can be defined as simply the time delta between when the event actually occurred and when the event was supposed to occur, with an event usually describing a rising or falling edge.

Jitter concerns

While designing a SERDES application, should a designer be concerned with jitter? It is important to remember that the link between the serializer and deserializer is fixed. All drive amounts and jitter are set by the type serializer. However, in order for the serializer to provide a clean signal to the deserializer, a tight clock must be provided. This specification appears in serial izer datasheets as tJIT and applies to the TTL signal coming into the TCLK pin of the device. The way this jitter value is specified can vary between vendors so a call to the respective vendor may be in order.

Naturally, the designer wants to pay close attention to not introducing any further jitter to the SERDES link. Common differential design techniques include: matched trace lengths, close coupling, and tightly controlled impedance (100* for LVDS signals). When placing bypass capacitors for each device, using several vias and keeping power traces wider than typical signal traces can decrease inductance.

A demo board designed by Fairchild Semiconductor Ensigna Lab was used for all empirical data. Several different length cables were constructed of CAT-5 cable and placed between the serializer and deserializer devices for the 10:1 family. In each cable only one of the four twisted pairs was used with an RJ-45 connector on each end. Due to the density of CAT-5, a maximum of four 10:1 devic es could transmit over a single cable. If each of the devices were operating at their max transfer rate of 660 Mbit/sec, a single cable could maintain 2.64 Gbit/sec.

The media was composed of 100* unshielded twisted pair (UTP), though a shielded cable will provide increased signal integrity. The oscilloscope has the horizontal resolution set to show only a data bit eye diagram for the first 4 data bits. Scope acquisition is set to infinite persistence to show jitter and a differential probe was used, which actually measures the absolute differential between two traces regardless of their polarity. Therefore, the waveform amplitudes are read as double what the independent waveforms are.

It is important here to point out the data dependant jitter on some of the rising and falling edges. The TTL data sent to the serializer is not a simple one/zero combination that repeats. Data used in each of the scope plots is "random" in nature. Ten vectors containing a wide variety of one and zero combinati ons were generated and repeated. Therefore, data dependant jitter exists in the plots, which is evident by two distinct falling edges on bit 1 below. A device employing 8B/10B encoding would minimize this type of jitter.

In any design, the only way to know if the eye pattern is large enough for the strobe positioning for the deserializer is to use a Bit Error Rate Test (BERT). When comparing two vendors IC's it is important to use the same data pattern, perhaps a standard K28.5 pattern.

SERDES devices have been around for over five years, but until recently have had little visibility as a true interface device. Due to the recent surge in LVDS technology and the realization of its common mode versatility, SERDES now has an excellent partner for future expansion. With some vendors already releasing full duplex devices, expect to see larger throughput and much larger packages in the BGA variety.

As redundancy becomes increasingly popular, newer SERDES releases will be similar to the FI N7216-01, Fairchild's new Quad 8-bit SERDES device, that offers completely redundant data communication with unlimited timing control. Expect to see more encoding schemes adopted and more elastic buffer implementation. Regardless of the device features, understanding datasheet specifications and applying that performance to the design at hand will always be required.