IP users plead for better verification

IP users plead for better verification
By Anthony Cataldo, Semiconductor Business News
January 30, 2003 (11:53 p.m. EST)
URL: http://www.eetimes.com/story/OEG20030130S0060

Santa Clara, Calif.-SoC designers have many reasons to be skeptical about intellectual property that they didn't create themselves, but none causes so much as angst as the thought of buying a core that doesn't work as it's supposed to.

Unfortunately for them-and the IP trade-IP verification is the single biggest problem facing third-party cores today. And unless IP vendors do a better job of proving that their products work in silicon and as part of a larger system architecture, it won't get much better either, said a number of users here at DesignCon.

"The verification task is enormous," said Michael Dini, president of The Dini Group, an engineering firm in La Jolla, Calif. "Once we've obtained a piece of IP, to then take some other blocks and put them together and make something work is 80 percent of the task."

That means SoC developers oftend wind up doing most of the verification work themselves or spending time on the phone with an I P vendor trying to track down someone who can rescue them. In either case, the problems that third-party IP are supposed to solve-namely, the time it takes to go from specification to chip sampling-could end up getting worst, panelists said.

Randy Rhodes, chief executive officer at San Diego-based design house Octera Corp., knows what it's like to get burned. He recalled one instance when his company bought a third-party core that turned out to be a verification nightmare. "We spent twice the cost verifying it that it would have taken to develop the IP ourselves," he said.

Since then, he's learned to stay away from cores that claim to be "user configurable," that don't have solid verification credentials and that haven't already been proved to work in silicon.

"Preferably you don't want to be the guinea pig. You want something that's working in silicon," he said.

Venkat Iyer, vice president of engineering at contract engineering company Comit Systems (Santa Clara, Calif.), agreed that it can be risky to use IP that hasn't been throughly scrutinized beforehand. "You don't want bleeding-edge IP because the design cycle time is longer," he said.

Aside from taking early precautions, Iyer said it's important to verify the IP at many points in the design process, including RTL, gate level, pre- and post-layout stages. Having a firm grasp of the chip's architecture before starting the design is another must. It's also helpful to find a way to generate documentation automatically since "engineers are averse to documentation," he said.

Beyond that, panelists said IP vendors themselves need to do more to ease the verification burden. Mark Beal, chief technology officer at design services company Intrinsix Corp. (Westboro, Mass.) said IP vendors should go beyond making assurances that the stand-alone core works as promised.

"There needs to be a big push to deliver extensible, verified IP that's usable in the system, not just to prove that the IP delivered still works," he said.

IP v endors also stand to improve their customer support teams, which panelists roundly critized for being unresponsive and lacking technical depth. Dini said it's not uncommon to get passed on to someone who can't answer his questions. "It's usually the new guy," he said. "Rarely are you allowed to talk to the engineers that created the IP."

And IP vendors aren't always consistent in how they distribute the IP. Sometimes it comes in VHDL, other times in Verilog and still others provide net lists. But if users aren't given access to the source code itself, it can be difficult to reach timing closure, Dini said.

Aside from technical concerns, some panelists questioned whether independent IP vendors were clinging to a flawed business model as many of them have either closed down or are struggling to get by.

Indeed, there's too much bad IP going around to inspire much confidence. "There's a lot of poor, unproven IP products and a lot of people have been burned by that," Rhodes said.

Rhodes, for o ne, doesn't think the IP industry will take flight until EDA companies develop the tools "that give you the same confidence as if you're buying a component."

But don't bet on it, Dini retored. "The EDA industry doesn't have a really good track record when it comes to listening to users," he said.

Despite their doubts, some panelists pointed out glimmers of hope for the IP trade. Though they are being more cautious, none said they would stop using third-party IP outright. And when done right, some admitted that third-party IP works wonders in reducing chip development time. Rhodes said his company was able to spin out one design in less than 10 months by exploiting re-usable IP.

"IP can work," he insisted.

And there are indications that third-party IP is here to stay. Xilinx, the leading FPGA vendor, has developed an IP interface that will work with IP generated internally and from outside sources, said Reno Sanchez, Xilinx's IP engineering site manager. And IP has shown that it gets bett er with time. The process of testing an IP core, for example, is no longer the huge problem it was several years ago, Beal said.

"I don't think the re-aggregation of the industry-where IP and silicon comes from the same vendor-is the right answer," Beal said.