The Complicated Chip Design Verification Landscape

By Bipul Talukdar, director of applications engineering for North America, SmartDV

While a working device that meets all functional specifications is a chip design project group’s No. 1 goal, many designers wake up covered in sweat worrying about a dead-on-arrival chip. No matter how much coverage or how many verification tools are employed, a bug or multiple bugs could slip through the net.

This high-pressure, demanding engineering environment requires three independent technology-based verification tools at the functional level to guarantee a bug-free functional and highly reliable chip. The overlap in verification and test coverage may seem to be excessive. Many sleep-deprived designers believe the additional effort is worthwhile.

The three functional-level verification steps –– functional verification, functional test, and built-in self-test (BIST) –– each offer a sense of confidence in the chip’s design. Combining them triples the sense of confidence that the chip will work as the functional spec intended.

Functional verification is the most resource-hungry step because it uses an abundance of available EDA tools and plenty of the hours budgeted for verification. Functional verification must encompass both functional coverage and code coverage. The two approach the verification problem differently and are necessary for ensuring comprehensive verification.

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