Synthesizable analog IP key to embedded SoC platforms

And, they may provide either functional and infrastructure IP, or both, as well as definitions and interfaces for layers of abstraction in the design process. Functional IP may include microprocessors, DSPs, specific logic functions, mixed signal, memory and interfaces (USB, serdes). Infrastructure IP may include clock and power network architecture, cell libraries and test setups.

The intent of such platforms is to enable rapid customization of complex chip designs. This is typically accomplished through modifications in software or small blocks of logic, while the functional IP is basically static.

However, the key to making platforms truly flexib le, and a vehicle for highly differentiated semiconductor products with fast development time, is to make the functional IP rapidly customizable. There are already companies offering configurable memories and processors, as well as firms offering libraries of such functions. These capabilities are seeing significant adoption for complex chip designs.

The most difficult functional IP to render customizable, and an integral part of such SoC platforms, is the analog and mixed signal blocks. These functions are tied very closely to process technology and vendor, and have for years resisted not only configurability, but also even the accumulation of a library of functions — due to the difficulty and time to implement an analog function in a target process.

This is particularly problematic in light of the now well-documented increase in analog content in SoCs, a trend that will only accelerate. The fastest growing part of SoCs, and that which has in many cases the greatest potential for diff erentiation, is the most resistant to configurability.

Limited innovation in analog design methods has been a primary cause for the lack of customizable analog solutions. Developments in synthesizable analog IP are changing this state of affairs, however.

It is now possible to very rapidly (minutes to hours) synthesize a complex mixed signal function such as a PLL, op amp or data converter, from specification direct to placed & routed GDSII. This type of IP has been proven in silicon in 0.18 and 0.13 micron CMOS and can make a huge contribution to the utility of platform-based design.

With synthesizable analog IP, a platform-based designer can now not only customize the analog and mixed signal sections of the chip, but they may adapt these circuits to changing chip level requirements up until a few week before tapeout. This is in contrast to current practice where analog IP is totally fixed and the design must accommodate the IP.

Interestingly, in all of the considera ble public discourse regarding application platforms there is little discussion of the analog/mixed signal aspect of platform development and use. While there are certainly numerous important and difficult problems to solve around processor programming, bus architectures, RTL coding and the like, the analog content of platforms merits much greater attention than given to date, for a couple of important reasons.

First, integration is a key driver of the complexity management imperative fueling platform-based chip design, and with integration inevitably comes analog functions as it reaches the edge of the system. Also, the key applications in consumer, communications and computing/storage that can economically justify platform development are analog-intensive. As integration progresses, analog is always at the edge in these types of systems.

Multimedia interfaces, high-speed interconnect and clock distribution and communications transmit/receive channels are all mixed signal subsystems, and are very often key components of an application system platform.

There are a variety of types of application platforms available in the market today, each with varying degrees of analog-friendliness: standard product chip based, semi-custom chip based and semiconductor IP based. Of the three, the semiconductor IP based platforms, which are not committed to specific underlying silicon, offers the highest analog flexibility.

Components in platforms

The role of analog in the definition of first generation application platforms has been either non-existent, or inflexible, depending on the type of platform. Analog is in some left to be implemented separately by the system designer, as in standard product-based approaches, or with some technology-based IP approaches. In others, such as semi custom product-based approaches with fixed IP blocks, a fixed analog IP block is provided.

The problem: it leaves the analog portion of the system out of the platform paradigm. It cannot be flexed during system-level tradeoff analysis as can digital circuits. This is because it is either not present in the system architecture provided, present by an inflexible block or present in the form of a high level model which cannot reliably represent what is achievable at the next layer of abstraction down.

In these cases, time to market is lost due to the requirement to handle analog separately, outside the platform-based design methodology, or flexibility and the opportunity to differentiate in this part of the system is lost. Further, the return to the developer is diminished; the system platform is either incomplete (where analog is not included), or the inflexibility of the analog subsystem limits the range of use of the platform.

As integration continues in the analog-intensive applications that are the target of platform development, this exclusion of analog/mixed signal from the platform paradigm becomes more costly, compromising the key benefits of the p latform approach.

We can define configurable analog components as blocks which can in some fashion be expressed at a high level of abstraction and reliably be converted in an automated way to a lower level (physical) implementation. In an application platform-based design approach, these would take the form of one of the semi-flexible system-level elements available to the user. It is semi-flexible in that it can perform a range of performance specifications, but has some limitation in range of function or architecture.

There are other existing types of semi-flexible, or synthesizable components that are seeing use in platform based design. These include configurable memory from companies such as Virage Logic and configurable processors from companies such as Tensilica. In all cases, these types of components offer flexibility and time-to-market in exchange for the some limitations on architecture, and the use of proprietary configuration systems.

A variety of approaches have been taken to bring configurability to analog blocks. These include analog arrays, metal configurability/tiling, simulation toolkit-based analog and geometric programming- based analog.

Analog arrays provide an array of transistors that can be configured with metal. This approach suffers from cost and performance limitations imposed by the array structure, is not a good candidate for platform-based design. It also offers limited ability to program at a high level of abstraction.

Tiling of lower level blocks achieves better performance and cost than arrays, and can be programmed based on performance-level abstraction reliably. However, they cover a very narrow range due to the fixed nature of the analog sub blocks, and offer little flexibility. .They are best suited to platforms where very little value comes from the ability to change the analog block. This approach is best suited to metal-only programmable solutions such as FPGAs.

Hard analog IP blocks are another alternative. Hard IP d oes enable abstracted levels of design due to availability of higher-level models, and can sometimes be made configurable such as through programmable bits in a PLL. Programmable PLLs can be used within an analog block with elements such as converters to enable a level of flexibility. The trade-off is that there is usually an area penalty to using such a block and this directs results in cost inefficiencies that make this a non-viable solution for platforms since platforms are best suited for high volume cost-sensitive end-user applications. This approach can be applied to a variety of platform types.

Fast and reliable

Geometric programming-based (GP-based) analog components rely on the coding of circuit and process characteristics into a geometric program. Then a solver is used to synthesize the physical circuit that will achieve the users system performance specifications. This approach is functionally limited to whatever circuit/process combination has been coded, but offers a reliable system programming level of abstraction, and very fast (hours) implementation times. It also readily enables system performance tradeoffs and is broadly applicable to a variety of platform types.

Thus, while there is a range of options for configurable analog IP, it is clear that GP-based synthesizable analog IP offers significant advantages for frequently used functions. As a focus of application platforms is on very specific types of systems, where the same types of functions are likely to be used repeatedly, there is a very good fit.

In the development and provision of application platforms, the use of synthesizable analog IP has important implications.

For one thing, the range of applications that can be targeted in an application platform business plan can be significantly wider using synthesizable analog IP than with hard analog IP. Instead of using a single fixed block, or a selection of blocks (most of which would be unused), a single synthesizable bl ock can be instantiated in the platform, covering a wide range of possible system performance specs.

Further the solution can be more complete than one that does not include the analog subsystem at all. Together, these translate into higher design wins and/or higher value and pricing. Also, the use of synthesizable analog IP enables the designer to build in powerful analog system tradeoff capabilities in an integrated flow.

There is also the issue of how often there is a need for the provider of semi custom product-based application platforms is to tweak or change certain fixed elements of the platform to meet key customer requirements. When these changes are needed for the analog section of the platform, long design and verification cycles are involved, possible even a silicon spin.

With the use of geometric-programming based analog IP, the modification of the analog section is push-button. The circuits generated by this method are correct-by-construction and are thus pre-verifie d and reliable. This results in dramatically lower support costs.

The use of true synthesizable analog IP, such GP-based IP, makes the analog subsystem truly programmable, bringing the analog domain of an application platform into the same system design paradigm as the digital domain. It is possible to go from a system performance specification reliably and directly down to the implementation level of abstraction.

This article was excerpted from ESC paper 341, titled "Application Platforms and Synthesizable Analog AP."

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