Reconfigurable computing arrays challenge DSPs

Reconfigurable computing arrays challenge DSPs
By Ron Wilson, EE Times
April 28, 2003 (5:17 p.m. EST)
URL: http://www.eetimes.com/story/OEG20030428S0054

San Mateo, Calif. - For a number of good reasons, reconfigurable computing array architectures have been drawing more attention of late. In these designs, a large array of processors-usually from several dozen to several hundred cores-are arranged on a chip. The function of the cores, their configuration and their connection into the interconnect matrix that surrounds them are all programmable. Vendors and some researchers contend that such an array of processors can execute many algorithms much more efficiently than can even a very powerful DSP chip. And since the array is programmable, it is much more flexible than a traditional ASIC.

Most approaches to such computing fabrics have been standard-product ICs. But at least one vendor, Pact XPP Technologies AG (Munich, Germany), has offered an array as synthesizable intellectual property intended for incorporation into a larger system-level ASIC as a coprocessor. That raises an interesting questio n: What is it like to implement a processor fabric for high performance? How does it differ from traditional ASIC data path design?

The answer from Pact is that the design, while not trivial, is neither more difficult than any other part of ASIC design nor fundamentally different in tools or flow.

Pact product manager Eberhard Schueler, together with program manager Paolo Mancini and senior consultant Giovanni Martinelli, both with design services house Accent Srl (Vimercate, Italy), trace the implementation of a chip-level Pact processor array. The bond-out chip was fabricated using STMicroelectronics' 0.13-micron, six-layer copper process.

As Pact had said, the design required only standard tools-in this case primarily from Cadence, a partner in the Accent joint venture. But there are some points of emphasis to consider, the authors say.

First, the Pact architecture is an array of arithmetic logic units, not of full computers. It is necessary to parameterize these ALUs, sele cting their word width and operation set before design can begin. The size of the array and mix of ALU, memory and I/O blocks also has to be determined. This was done by extensive simulations across a range of communications tasks, chosen to represent end-user tasks.

With the array characterized, a normal Verilog-based design flow can begin. But again there are differences. One major point is that the design is inherently hierarchical-it is, after all, a regular, nearly homogeneous array. Designers should exploit that at every level, the authors say.

The authors show how initial simulation work to determine critical-path requirements provided a set of timing constraints that guided all the rest of the design stages.