Configurable logic IP brings flexibility to SoCs

Configurable logic IP brings flexibility to SoCs
By Ron Wilson, EE Times
May 12, 2003 (1:59 p.m. EST)
URL: http://www.eetimes.com/story/OEG20030512S0027

San Mateo, Calif. - Another entrant in the fast-moving structured-ASIC market, ViASIC Inc., this week will introduce intellectual property (IP) to produce a base array and a tool to map logic netlists onto the logic array architecture. Unlike most other structured-ASIC suppliers, ViASIC will focus initially on logic arrays embedded in larger, system-level ICs, not on standalone ASICs.

ViASIC's products are based on an array of complex logic cells interspersed with distributed memory structures-a combination not used in other structured ASICs announced so far (see May 5, page 18). The logic cells are fairly coarse-grained, with a flip-flop, four NAND gates, two multiplexers, a large buffer, some inverters and a diode for antenna-effect control. In practice, implemented cells average just over 11 equivalent ASIC gates, said Bill Cox, chief technology officer at ViASIC (Durham, N.C.).

Memory for the array is organized into 256 x 16-bit stru ctures, Cox said. But uniquely, these structures are not implemented as standalone blocks; rather, they are interspersed, column by column, throughout the array. The bit columns are designed to permit over-the-top routing-a decision that required careful bit-line and sense-amp design, Cox said-so that the memory area, instead of being lost to logic, is in fact a routing resource.

The key to low nonrecurring expense and fast turnaround is ViASIC's interconnect design, which uses single-mask programming. All of the metal layers are predefined except for the via layer between Metal-3 and Metal-4. The metal patterns are planned so that the logic cells can be configured, the memories organized and all of the components interconnected by using this one via layer to link the predefined metal patterns on M4 and M5. The patterns also permit an arbitrary number of user-defined clocks. Power/ground and scan chain connections are preestablished.

The technology is conceptually similar to that of e-ASIC Co rp. (San Jose, Calif.), which also supplies single-mask programmable IP to system-on-chip developers. But the e-ASIC cell includes memory and can be configured as a logic cell, memory cell or SRAM-programmed programmable-logic cell. ViASIC's cell is intended for logic use only, and its architecture includes dedicated memory structures.

In practice, ViASIC provides the physical design for its base array and the proprietary ViaPath software tool for mapping gate-level netlists onto the array. The contract includes one logic array "footprint," designed to a customer's requirements, which the customer includes in its design flow as hard IP. The array can be programmed as necessary using the via mask.

Initially, ViASIC will target sophisticated SoC design teams that want to add an area of configurable logic to their larger design. This is typically done to permit one SoC to span a range of product configurations or to adapt to changing algorithms, said Max Lloyd, ViASIC's chief executive officer. The company has already engaged in such designs, he said, and has talked with a number of other design teams.

The ViASIC array has been implemented in the 0.18-micron logic process of Taiwan Semiconductor Manufacturing Co. Plans are under way for a 0.13-micron implementation as well.

Looking ahead, the company hopes to work with a foundry partner to offer a line of full-chip ViASIC arrays. Lloyd claimed the company's technology offers the best logic density available on the market.

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