Extending network-on-chip (NoC) technology to chiplets

By Frank Schirrmeister, Arteris
EDN (November 15, 2023)

A monolithic integrated circuit (IC) is one in which everything is implemented on a single silicon die, also called a chip. The maximum practical size for a die using extreme ultraviolet (EUV) lithographic process is around 25 mm x 25 mm = 625 mm2. Although it’s possible to build larger dice, their yields start to fall off rapidly. So, one solution for today’s multi-billion transistor devices is to disaggregate the design into multiple smaller dice mounted on a silicon interposer, presented in a single package. In this case, the smaller dice are referred to as chiplets or tiles, while the final device is known as a multi-die system.

There are multiple advantages associated with adopting a chiplet-based approach. These include increased yield, reduced die cost, and the ability to implement different functions on optimal process technologies. Also, there are increased flexibility and customization options because designers can pick and choose the appropriate chiplets for different applications. This method delivers increased scalability because more chiplets can address higher workload demands and reduced time to market by reusing existing chiplets in various combinations across different products.

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