Advanced Topics in FinFET Back-End Layout, Analog Techniques, and Design Tools

By AsicNorth

In our last post, we looked at the basics of finFET technology and how its increased complexity and constraints influence layout design choices. In this post, we’ll look at more advanced technology topics and key design tools that enhance layout productivity. We’ll also explore what might be next for integrated circuit (IC) mask layout design.

Multi-Patterning

The metal layers at the bottom of the stack, closest to the devices, must be on-pitch or very close to both the fin and poly pitch. This means the metal pitches for these layers should be among the finest geometries the process can support. Modern technologies achieve this with a multi-patterning technique known as self-aligned double patterning. More complex approaches requiring triple- or quad patterning are also practiced.

Double patterning requires shapes in the first few layers of the metal stack to be “colored,“ with the different colored shapes on a given layer being masked and deposited at different steps in the process. The coloring can be done algorithmically after the design is complete, but most often in custom IC layout, the coloring is done manually to maximize density and optimize electrical characteristics.

For example, the minimum pitch of Metal1 ColorA might be 50 nanometers (nm). Alternating Metal1 ColorA with Metal1 ColorB might allow a pitch of 25 nm, effectively doubling the metal density and current–carrying capability.

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