System-on-chip (SoC) design is all about IP management

By Efren Brito, Faraday Americas
EDN (June 13, 2024)

For most system-on-chip (SoC) designs, the most critical task is not RTL coding or even creating the chip architecture. Today, SoCs are designed primarily by assembling various silicon intellectual property (IP) blocks from multiple vendors. This makes managing silicon IP the dominant task in the design process.

Generally, less than a tenth of a new SoC design will be newly written RTL code. And often, the high-level chip architectural decisions will be clear: a variation on an existing architecture or a reflection of major data flows in the application layered on a standard bus or network-on-chip (NoC) structure.

But each piece of IP in the design—and there may be dozens of types and hundreds of instances—requires management. The chip designers must define requirements, select vendors and specific products, make any necessary customizations, set configuration parameters, and integrate the IP instances into a working, testable system. This process will consume most of the project resources until physical design.

This reality makes expertise in managing IP a significant factor in the success of an SoC design. Perhaps less obviously, access to IP—particularly the ability to get attention, detailed specifications and documentation, bug fixes, and customization support from large, influential IP vendors—becomes a critical issue. The growing complexity of the IP blocks only adds to the challenge.

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