Understanding the contenders for the Flash memory crown

By Eran Briman, Weebit Nano
embedded.com (July 5, 2024)

Much like the end of Moore’s Law, the scaling challenges of flash memory have been a significant issue for several years. Embedded flash memory is reaching its limits as technology nodes for embedded applications shrink below 28nm, necessitating the reduction in the physical size of flash memory cells.

This miniaturization challenges the basic mechanism of charge trapping found in flash and other non-volatile memory (NVM) derivatives, making manufacturing at these smaller nodes extremely expensive and impractical for embedded applications.

Additionally, even at nodes where embedded flash is viable, flash memory cells have limited endurance; they can only withstand a limited number of program/erase cycles before degradation occurs.

Flash also consumes more power than alternative NVM technologies like MRAM and ReRAM. Power consumption is a critical factor in embedded systems where energy efficiency is essential for extending battery-life. In the case of power management and other high-voltage applications, customers are using a BCD (Bipolar-CMOS-DMOS) process flow that is far more sensitive to modifications in the FEOL (Front End of Line), such as those required by flash. Power devices tend to be more cost sensitive, and flash, typically requiring 10 extra masks, is very expensive to manufacture, adding 20-25% added wafer cost.

However, emerging NVMs like MRAM and ReRAM offer advantages that align better with the requirements of advanced embedded systems at smaller process nodes. These technologies also threaten to disrupt the market for embedded flash at more mature geometries, such as 40nm, 65nm, and even 130nm. This is significant for many vendors, especially in mature nodes, which are highly price sensitive.

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