Analysis and Summary on Clock Generator Circuits and PLL Design

By Shivani Gupta, Sr. Verification Engineer -1, VeriFast Technologies

The demand for analog and mixed-signal-based integrated circuits (ICs) has surged due to the increasing reliance on electronic-based applications across industries. As the world transitions to more advanced technologies, low-noise, low-power systems have become highly competitive in achieving optimal design performance. Among the most critical components are clock generator circuits, which require low phase noise and low jitter for high-precision operation.

Challenges in Clock Generator Design

Jitter is one of the primary challenges in clock generator circuits. It arises due to the mismatch between the charging and discharging currents of the charge pump in a Phase- Locked Loop (PLL). This mismatch affects the control voltage of the Voltage-Controlled Oscillator (VCO), leading to instability and performance degradation. Additionally, supply noise can exacerbate skew and jitter in the system.

To improve the performance of clock generator circuits and mitigate these issues, the Phase- Locked Loop (PLL) architecture is widely used. A PLL can provide high synchronization accuracy and stability for high-speed, low-power System-on-Chip (SoC) designs.

The primary concern in PLL design is maintaining a stable control voltage for the VCO, as it directly influences the PLL's frequency and jitter performance. Variations in the mismatch between the charging and discharging currents of the charge pump lead to fluctuations in the control voltage, which, in turn, affects the frequency stability of the VCO.

Minimizing Charge Pump Mismatch and Jitter

To stabilize the VCO’s control voltage and reduce jitter, the mismatch between the charging and discharging currents must be minimized. Charge sharing within the charge pump is one of the significant contributors to this mismatch, leading to increased jitter. By addressing this mismatch, both the control voltage and jitter can be effectively stabilized.

Introduction to Phase-Locked Loop (PLL)

A Phase-Locked Loop (PLL) is a feedback circuit that compares the phase difference between the input reference signal and the output signal, adjusting the frequency accordingly to minimize this difference. This feedback loop helps generate stable clock signals in high-precision systems, such as radio communications, telecommunications, computing, and data recovery applications.

Figure 1 : Basic Block diagram of PLL

PLL Components

PLLs consist of five main blocks:

1. Phase Frequency Detector (PFD): Detects the phase difference between the reference signal and the feedback signal, generating an error signal.
2. Charge Pump: Converts the error signal from the PFD into current, which drives the control voltage of the VCO.
3. Low-Pass Filter (LPF): Filters out high-frequency components from the charge pump output, providing a stable control voltage to the VCO.
4. Voltage-Controlled Oscillator (VCO): Generates the output frequency based on the control voltage.
5. Frequency Divider: Divides the output frequency of the VCO to match the reference phase.

Types of PLL Architectures

Different PLL architectures are used to address the challenges in noise, jitter, and frequency stability.

1. Ring Oscillator-Based PLL

In ring oscillator-based PLLs, the VCO is typically implemented using a ring oscillator with a class-C configuration. To improve stability, an Amplitude Adjustment Circuit (AAC) is used to stabilize the VCO's amplitude. However, continuous operation of the AAC can lead to higher power consumption.

Figure 2: VCO with Amplitude Adjustment Circuit

This ring oscillator design often involves current starvation to reduce phase noise. In this structure, PMOS transistors are used, and the flicker noise power spectral density is inversely proportional to the oscillator's area. Optimizing the area of the current starvation structure helps minimize reference spurs.

Figure 3: Five-Stage Ring VCO with Vc Connected to Only One Stage

2. Dual Loop Dividerless PLL

A dual-loop dividerless PLL architecture helps reduce the noise contribution of the charge pump by increasing its feedback gain. The mismatch in the charging and discharging currents often generates reference spurs, which can be reduced by using a sub-sampling phase detector (SSPD). This design helps decrease in-band phase noise and improves overall performance.

Figure 4: Dual Loop Dividerless PLL

The Aperture Phase Detector (APD) directly senses the phase error between the reference signal and the VCO, converting it to an analog voltage via the Phase-to-Analog Converter (PAC). This results in a locked state when the charging and discharging currents are balanced in magnitude and phase.

3. Sub-Sampling Phase Detector-Based PLL (SSPD)

The Sub-Sampling Phase Detector (SSPD) eliminates the need for a frequency divider, which traditionally amplifies noise in the feedback path. In SSPD, the phase detector samples the error signal and generates a corresponding current based on transconductance (Gm). This current is integrated by the loop filter capacitor to control the VCO.

Figure 5: Sub-Sampling Based PLL

The use of sub-sampling minimizes noise and jitter by removing unwanted high-frequency components. This architecture also helps to increase charge pump feedback gain and reduce the overall jitter in the system.

4. Digital-to-Time Converter (DTC)-Based PLL

In DTC-based PLLs, digital-to-time conversion is employed to address non-linearity issues, which can lead to fractional spurs and noise. A simple comparator-based DTC gain calibration technique is used to reduce the dependency on multi-bit time-to-digital converters (TDCs). This helps minimize clock duty cycle distortion and improves PLL performance.

5. Charge Pump-Based PLL

Charge pump-based PLLs are known for their flexibility and low power consumption. These PLLs are suitable for low-power IoT applications due to their ability to avoid the use of inductors and provide high performance with minimal power consumption. A switched capacitor loop filter is used to save up to 10% in power, but care must be taken to minimize charge pump mismatch, as it can introduce high reference spurs.

Low Noise Amplifiers (LNA) for Noise Reduction

Low Noise Amplifiers (LNAs) are used to reduce the impact of supply noise and mismatch currents. By utilizing a complementary differential input technique, LNAs can help reduce input-referred noise. The Class-AB output stage further increases voltage swing and reduces ripple, which is critical for maintaining PLL stability and performance.

Conclusion

In summary, charge pump mismatch and jitter are the leading causes of instability in PLL systems. By minimizing the mismatch between the charging and discharging currents of the charge pump, the control voltage of the VCO can be stabilized, significantly reducing jitter.

Several approaches, such as ring oscillator-based VCOs, sub-sampling phase detectors, dual loop dividerless PLLs, and digital-to-time converters, offer potential solutions to address jitter, phase noise, and power consumption in PLL design. Low noise amplifiers also play a crucial role in improving overall PLL performance by mitigating supply noise.

Ultimately, the tuning voltage of the VCO is inversely proportional to the stability of the system, and for optimal performance, it should be minimized. By leveraging the appropriate PLL architecture and optimizing key components like the charge pump, VCO, and loop filter, designers can achieve high-speed, low-power, and low-jitter systems suitable for modern, high-performance electronic applications.

About the author

Ms. Shivani Gupta is an ASIC Verification Engineer with more then 3.5 years of working experience at VeriFast Technologies Inc.

Before Joining VeriFast she had done her Masters in VLSI & Embedded Systems from ABV-Indian Institute of Information Technology and Management.

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