What is JESD204B? Quick summary of the standard

By Chip Interfaces

The JESD204B Standard enables the establishment of high-speed serial links between a Controller and ADC and DAC converters with Deterministic Latency. JESD204B was first published in July 2011 and was the first JESD204 standard version to describe the deterministic latency mechanism. It is the next iteration of the JESD204A standard from April 2008 and retains most of its functionality while quadrupling the line rate and introducing other minor changes to accommodate the new features. It was followed by an incremental update JESD204B.01 in December of 2021 slightly increasing the maximum line rate. In this blog, we introduce the JESD204B.01 standard and its capabilities.

One of the significant changes made in this standard is the increase in specified Line Rates from an upper limit of 3.125 Gbps to 12.5 Gbps. This was done to accommodate the PHY capabilities introduced at that time. The increase in Line rate was still accommodated by the 8b10b encoding of the previous standard with optional data scrambling.

The 8b10b encoding uses Data Characters (D.x.y) and Control Characters (K.x.y), with /K/= /K28.5/ Comma Character being the most common one used for finding Word boundaries, but other control characters like the Frame Alignment Character /F/= /K28.7/ and Lane Alignment Character /A/= /K28.3/ are used for aligning lanes and JESD frames for data decoding. Finally some K Characters /R/= /K28.0/ and /Q/= /K28.4/ are involved in the initial synchronization handshaking.

During link startup the Receiver (RX) handshakes with the Transmitter (TX) with the use of the 1-wire sync signal and a data sequence called Initial Lane Alignment Sequence (ILAS). This allows the RX to control the start of data transmission and align it with its ready state. When the receiver requests synchronization by pulling the sync signal low the Transmitter is instructed to send a constant stream of /K/= /K28.5/ characters such that the receiver can align the bit stream to 10-bit word boundaries. At this point, the Receiver releases sync to high, and the Transmitter can use the next Local Multi Frame Clock (LMFC) boundary to start transmitting the ILAS.

This special data sequence consists of an incremental counter value for each Data symbol and lasts for 4 or more Multi-Frames. The first character of each Multi-Frame in ILAS is a Start of Subsequence Character /R/= /K28.0/ and the Last character is a Lane Alignment Character /A/= /K28.3/. The second multi-frame however instead of the incremental pattern contains the Start of Link Configuration Data Character /Q/= /K28.4/ followed by the link configuration data of the Transmitter. In future iterations of the standard sync signal were removed to simplify the design and the handshaking was replaced with the mechanism of a self-synchronizing receiver.

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Deterministic Latency introduced in this revision of the standard allows for the Link Latency to be constant despite latency variations on the serial link, also with the capability to finely adjust it to meet broad system synchronization requirements.

Deterministic latency is achieved by the use of a Buffer in the receiver which compensates for latency variations on the serial link and often serves the dual purpose of de-skewing lanes. JESD204B introduces the concept of subclasses, with subclass 0 having no deterministic latency, subclass 1 achieving deterministic latency with the use of SYSREF, and subclass 2 achieving deterministic latency with the use of the sync signal.

SYSREF is a signal which is distributed to all elements of the system and used as a common timing reference. Sync wire serves a dual purpose for initial handshaking but also allows the transmitter to determine the relative alignment of TX and RX multi-frame periods and adjust it. Keep in mind that the following iterations of the standard, and the removal of sync pin subclass 2 only appear in JESD204B.

Chip Interfaces’ JESD204B IP Core is an established, highly optimized, fully featured, silicon agnostic for ASIC and FPGA, interoperability tested and silicon-proven implementation of the JEDEC JESD204B.01 standard. To learn more about our JESD204B IP and how we can enable your project, please contact sales@chipinterfaces.com.