System-In-Package or System-On-Chip?

System-In-Package or System-On-Chip?
By Cynthia Trigas, EE Times
September 19, 2003 (12:20 p.m. EST)
URL: http://www.eetimes.com/story/OEG20030919S0049

System-in-package (SiP) has created a new set of design challenges. SiP designs are typically only attempted when a wall is reached-such as size or performance constraints-and conventional system-on-chip (SoC) solutions are too expensive to implement. The higher integration capacity of SiP reduces the number of components in the system and trims the size and routing complexity of the printed circuit board. However, SiP design poses challenges due to the lack of similar design infrastructure between semiconductor technologies and the multitude of layout possibilities. Packaging concepts include chip stacked on-chip, flip-chip stacked on-chip, chips placed side by side in a package, as well as other concepts. These complicate the design partitioning process.

So how does one optimize a design? Optimizations need to happen at the system level to reach the next level of cost optimization. The industry is going from the “quests for local optima” to the “ quest for the global optimum”.

Designers need to evaluate whether to place discretes on the chip, on the module or on the customer printed-circuit board. As the application frequency increases, designers must place these discretes closer to the active circuitry for adequate system performance. Other factors which could influence the partitioning are increasing functionality in multiband or multimode applications, increasing battery life, lower sales price-despite new features being added-and decreasing part count, size and weight.

A design usually starts with a system requirements analysis, followed by the design on the system level. Subsequently the system is partitioned into its components and the components are then designed and developed. The components are manufactured, tested, and parts are assembled and the system is retested. Finally an acceptance test by the customer is required. In a real development process this design flow is not so straightforward. Problems appear during the component, s ystem and acceptance tests that must be solved. These recursive loops are time consuming and costly. The only means of reducing these redesigns is to use simulation techniques during the early phases of the design process before manufacturing the components. This is especially important during the partitioning analysis.

Additional cost enhancements can be obtained by comparing the technical and performance advantages between single-die and multi-die solutions. Relative costs based on defect density scales with area, therefore there will also be a crossover decision on when to use a one-die solution vs a multi-die solution. To integrate different technologies the wafer fab must create new process steps. This can increase mask costs and cost of wafer processing due to the increase in the defect density from additional process steps.

The combination of more masks, more defects, and larger die escalates the costs per die. One example of this is the reduction of on-resistance in power devices for full br idge applications. A single-die SoC solution can be cost effective when the MOSFET on-resistance is not required to be low-for instance, in lower-current applications. In higher-current applications where low resistance is needed, a multiple-die solution is more cost competitive.

Comparisons must also include the technical improvements in substrate technologies. A silicon-based substrate using copper/low-k interconnects defined by lithographic process on silicon offers dense routing with high speed, and low-noise signal paths can be used with embedding and chip stacking. The ICs can then be designed to leverage the high-density interconnect by optimizing both the core and the I/O of each device. Additionally, specialized devices can be designed specifically for the SiP architecture to take advantage of the high bandwidth and low latency features. Reducing chip-to-chip bus capacitance can thereby dramatically decrease system power requirements and thermal dissipation.

High-end applications such as W LANs offer another example of how a system fully integrated on a single chip (SoC) still contains performance pitfalls. For instance, the maximum output power to be delivered by the power amplifier still remains a critical issue for standard silicon. Some other elements of the front-end, like the transmitter/receiver switch, the RF filters or the voltage-controlled oscillator (VCO) tank, may also be hard to implement in standard silicon technologies. Noise isolation and technology fusion of analog/RF with digital and memory systems can be costly if poorly analyzed whether as a SoC or a SiP.

Key challenges of early performance estimation for system implementations include:

Lack of physical layout information;

Lack of accurate models for emerging issues such as mixed-signal isolation, technology fusion, and IP module integration;

Lack of accurate and efficient computation algorithms since most of the systems are inherently complex, which may consume extreme memory and CPU in a full simul ation.

An iterative process of examining all partition placements, isolation techniques and associated costs should be made. In reality, time-to-money constrains all possible partitioning from being examined. The advantages of SoC are good performance, small system size, and potentially low system cost. However, in a mixed-signal system, SiP is an attractive solution due to clever chip partitioning which can remove substrate coupling problems and improve chip yield by partitioning a large system into several chips.

The semiconductor industry challenge is to be involved during the definition of the specification at the system and module level. This is critical whether designing a SoC, a SiP or a combination of both. The semiconductor designer has little training on the module level. Concurrent design teams from different areas using multidisciplinary approaches confront tool sets that do not communicate seamlessly for full system evaluation from the cellular level.

Performance cues

Whe n deciding whether to stack die, the I/O and electrostatic discharge (ESD) structures should be taken into account on each die. ESD is still a factor, even if the I/O is not connected externally to the package. At least a 500 V protection structure must be included to prevent accumulate damage during the manufacturing and assembly processes. Other factors to consider in I/O structures are the required drive strength of off-chip memories, which must be adjusted for a lower drive level. Features such as a 10 nF capacitor are also useful when added to the package on the VDD supply line just for noise protection.

For many applications stacked-memory die is an easy option. However, at 60 MHz, a SiP vs SoC decision can result in a 35 percent to 40 percent reduction of the main system performance if careful design practices are not employed. For instance, the average performance can be improved if a cache is added. By using a manual cache some of the critical routines which affect the performance can be overc ome.

Crosstalk must also be analyzed due to capacitive coupling effects and closely located bond wires which affect clock speeds and delay times. The inductance can also be bad for switching loads due to fly-back currents. Flip-chip attach technologies have lower inductance than wire-bond attachment and can thereby improve these design issues. However, the low inductance using flip-chip attach technology may also contribute to higher emissivity, so tradeoffs must be analyzed. System and packaging costs can be decreased by proper design that allows removal of decoupling capacitors and lower overall inductance. This is especially important at higher frequencies as the effects become worse.

Thermal performance must also be evaluated in relation to placement and orientation of die in a SiP configuration. In a stacked-die configuration, about 96 percent of the heat is dissipated through the board, thus the connection to the board and the copper coverage of the board are important design parameters. You'd expect the middle dies to experience the highest junction temperature since they are surrounded by heat sources. However, the top die usually has the highest junction temperature. Since most of the heat flows from the heat source to the boards, the distance from the board becomes the primary factor in determining the temperature gradient along with the package thickness.

The junction temperature distribution suggests a means to improve the thermal performance of a stacked package. When combining devices with different power levels, the high power device should be placed at the bottom of the package. This can influence the choice of packaging technology used to obtain an optimum thermal performance.

During reliability testing one should keep in mind the importance of matching the suitability of the test to the given application. Accelerated thermal cycling or higher temperature/stress testing which aims to shor ten the test time with more severe conditions can damage the materials used in the system, without answering whether the device will operate over the use conditions. The failure mode should duplicate the expected failure mode from a real-life test.

Unified designs

Unified hardware and software designs as well as data management are critical for both SoC and SiP. Layout-driven vs. specification-driven flows must be considered. Designers desire both a schematic and layout driven bi-directional interface. Even within a SoC design there may be different libraries. Quality of top-level instantiations can be compromised due to clashing of different versions within the simulators used. Links between IC layout and module layout are needed. Module and IC libraries in the same environment would allow optimization of the IC and system/module design on the fly. Reconfigurable platforms to analyze options based on alternative technologies are key to optimizing the design. Licenses cost money, so choices i n tools are continually being made that complicate the design-flow strategy.

For system-in-package design, component synthesis is needed for resistors, capacitors, inductors and transmission lines. The power and ground nets of the standard packages can be extracted from existing full-package design files (if they exist) and compared. However, analyzing the variations due to mirrored imaging of flip-chip stacked die vs. wire-bonded stacked die arrangements may be an early challenge in the design cycle. Spice modeling is traditionally used for specific simulations between inputs and outputs of different die. As the speed requirement for the application increases, more simulations are required to verify timing and performance.

Back-annotation steps are needed from the design of the mechanical inputs and the electrical evaluation back to system level, ensuring that any changes made do not compromise the complete system's proper performance. For this back-annotation step you need appropriate behavioral models for system simulation. They can be obtained either by back annotating parameters or by generating reduced-order models. Next steps are the layouts of the mechanical and electronic parts of the system. Even at this stage changes are taking place, which need to be back annotated to the component level and also to the system level if necessary. For instance, specific capacitances not known prior to layout must be back annotated.

The advantage of this approach is the possibility of performing a special kind of sensitivity analysis, where you can determine certain measures for the influence of each model parameter to each functional parameter, providing insight into which influence is critical for a particular design. Knowledge about these critical influences at an early design phase is essential for keeping recursion loops small.

Semiconductor vendors need to build an infrastructure to efficiently respond to SiP challenges. A specific SiP design flow should be implemented with interface tools tha t integrate into the existing design environment. Developments and documentation of new design techniques and SiP training sessions for system and IC designers are required to make the design flow more attractive and useful. EDA vendors must define common multi-EDA/ multitool SiP flows, specify common interface and information formats, and drive specific capability increases and bug fixes.

Where can the line be drawn between a system on chip and a system in package? There is no conceptual difference between a SiP solution and a total system solution. The SiP concept opens many doors for new system and architecture innovations. Institutes and universities are already working on vertical integration of thinned stacked dies with integrated passives that effectively could be labeled as SiP or SoC technology. Which tools will be used for predictive engineering, which organization or company will provide the product and what testing will be conducted to evaluate the design are issues that remain the same regar dless of the technology. Our customers and competitors are pushing us to expand beyond the SoC concept, and contribute to the optimization of the total system.

To successfully deliver a total system solution, the semiconductor industry needs to master both SiP and SoC solutions. SiP and SoC are about integrating several technologies and functions that complement each other to realize the best system-level solution for the lowest cost and the highest performance.

Cynthia Trigas is with Motorola Semiconductor Product Sector, Advanced Interconnect Systems Laboratory (Munich Germany).