Vectorless test: best bet for high-speed I/O

Now, an approach called vectorless test is emerging that offers the best of both approaches: the cost-effectiveness of on-chip I/O BIST combined with ATE-based signal integrity measurements. Specifically, the concept unites ATE parametric testing with on-chip test content generation and compare, forming a synergy between silicon and ATE. The result is an economical optimized solution for high-volume manufacturing test designed into the silicon, using established electronic-design-automation techniques.

Traditional ATE architectures have the ATE providing source vectors and at-speed vector handling for mission mode tests. As frequencies continue to increase beyond the gigabit-per-second threshold, especially for high-speed I/O interfaces, the cost of providing this capability on the ATE becomes quite challenging in a high-volume manufacturing environment.

To minimize the reliance on ATE testing, many device manufacturers are using the combination of on-chip BIST structures and loopback modes. Because of the high levels of integration possible in today's silicon processes, the additional cost of silicon area on the IC is very reasonable.

Unfortunately, the BIST approach suffers from its inability to perform mission-mode parametric tests, which are becoming more important with the integration of high-speed I/O interfaces. With frequencies in the multiple-gigabit-per-second range, the signals can no longer be treated as purely d igital. Signal-integrity concerns such as timing jitter and level noise need to be considered to maintain adequate fault coverage and to meet required quality levels.

Best of both approaches

Enter vectorless test, a more synergistic approach that takes advantage of the best of both ATE and BIST. With it, the ATE effectively functions as an extension of the loop in the BIST/loopback. As such, the tester does not provide mission-mode vectors and at-speed comparisons; instead, it is solely responsible for the signal-integrity verification.

Since the vector generation and at-speed compare capabilities traditionally drive up the cost of the ATE channels, this dual approach allows a much more economical solution for high-volume manufacturing.

Here's how it works. The on-chip BIST circuitry provides test content at the required data rates, which then can be tested according to standard protocols in a loopback mode. The ATE will contribute by performing signal-integrity measure ments that cannot be achieved with on-chip circuitry.

The setup for the parametric measurements does not require vectors, hence the full name: vectorless parametric testing. The parameters tested depend on the application and can range from simple jitter generation, tolerance and receiver sensitivity to even more sophisticated parameters like data-to-clock skew.

How does this affect the designer? The designer now is responsible for creating the mechanisms on the IC to deliver test content for the functional verification of the device as well as the parametric testing to be performed on the ATE. The designer must generate the worst-case signal-integrity conditions by means of a killer pattern tweaked for maximum stress to the phase-locked loops. One definite advantage of this approach is that designers can leverage the same technologies used to design their SoCs for the testing of these circuits instead of waiting for newer ATE technologies to be developed.

Loopback channel

On the ATE side, the loopback path is then extended through more cost-effective loopback channel cards in the ATE that allow for pattern independent measurement of the required signal-integrity parameters and optionally allow access to dc measurement resources. This loopback channel card can be configured to measure signal-integrity parameters, such as jitter, and also allows the test engineer to tweak the parameters for feedback to the receiver. That allows testing of both the transmitter signal integrity and the receiver tolerance with the same card.

For the most cost-sensitive applications, it is possible to just offer a pass/fail measurement, further reducing the cost of the ATE cards.

There are various ways to implement a lower-cost parametric loopback test solution. Some solutions use jitter injection modules as an add-on to the design-under-test (DUT) board, but these approaches can suffer from the fact that the jitter injected varies with the data rate.

A more flexible app roach involves a tunable data eye conditioner, which allows for independent jitter and level adjustment (see figure, page 62).

Since this cannot be achieved with passive components on a DUT board, a dedicated loopback card in the ATE is a suitable alternative. This allows the user to program the data eye opening using the ATE software.

The synergistic approach of combining on-chip BIST with ATE-assisted loopback allows for a more effective solution of the high-speed I/O interface test problem than either can offer alone. Although it does require that designers develop mechanisms to support parametric and logic test, existing EDA capabilities can easily support the creation of those mechanisms.

The combination of BIST and ATE allows for a cost-effective high-volume manufacturing solution that maintains high fault coverage and quality levels for the analog measurements required by the new SoC devi ces.

Bernd Laquai is a test methodology research consultant in computation and communications semiconductor test R&D for Agilent Technologies (Boeblingen, Germany).