| Verification users are familiar with outsize promises and disappointing results. It's not necessarily that vendors of such tools haven't come up with compelling technology or useful ways of approaching the task. Rather, what has been missing are practical solutions that use the best of these approaches to provide quality results in a reasonable time frame and at an affordable price. Formal or static verification methods, for instance, do not require the generation of test vectors, but these tools cannot test design functionality. Only dynamic testing driven by testbenches can do so-especially when embedded software such as drivers, real-time operating systems and custom applications must be tested. Technologies proposed in the past few years-hardware verification languages (HVLs), functional verification coverage software and hardware-assisted verification-narrow the gap between designers' goals and the results obtainable from traditional logic verification, anchored in software simulation and driven by HDL testbenches. New test languages and C/C++ libraries of test functions dramatically increase designers' productivity in terms of the number of tests generated in a given amount of time. Functional verification coverage tools increase designers' confidence in the testbenches produced with HVLs. But those categories do not address the problem of reducing the amount of time required to apply those tests, and they cannot be used when developing embedded software. Only hardware-assisted verification can accomplish the task within a practical time frame. Unfortunately, its superior throughput has been thwarted by the soaring price of these systems. When ICs were below 1,000 gates, the most popular functional design verification method was a breadboard emulator. With it, a design could be verified and debugged in its target system environment before silicon was fabricated. Since the design was tested under real operating conditions, functional correctness was assured. But when IC complexity passed 10,000 gates or so, breadboarding became impractical. The breadboard emulator was replaced by event-driven simulators. A billion cycles
Still quite useful at the RTL or behavioral level, event-driven simulators allow accurate functional and timing verification, with the advantages of ease of use, relatively low cost and sophisticated debugging capabilities. They run out of steam on chip designs when applied at the gate level. The execution of 10 seconds of real-time in a million-gate circuit designed to run at 100 MHz would require the execution of 1 billion cycles. Even on the fastest CPU, with a generous cache size and plenty of RAM, that would take more than three years with an event-based simulation at 10 cycles per second. Hardware emulation has become increasingly popular as a solution to the run-time problems that afflict event-based simulation. Emulators deliver execution speed close to real-time, thus enabling their use as in-circuit test vehicles. But their prohibitive cost of ownership and unfriendly usage model have restricted adoption to large corporations in limited number. Given the advantages and disadvantages of each approach, the answer would appear to lie with next-generation hardware-assisted functional verification that merges the performance of hardware emulation with the debugging flexibility and ease of use of software simulation at the price of an event-driven software simulator. The result? More powerful verification technologies in the hands of more designers, accelerating the progress of innovation. Luc Burgun is president and chief executive officer of Emulation and Verification Engineering Inc. (luc_burgun@eve-team.com). http://www.eet.com | 
