| Ultrawideband technology has been selected to serve as the foundation for evolutionary extensions to several very successful protocols. However, the promise of ubiquitous, high-bandwidth (500-Mbit/second), low-power wireless connectivity can only be realized using low-cost CMOS technologies. Developing RF or mixed-signal integrated circuits entirely in CMOS makes it possible to produce chips on a large scale at low-cost, cutting-edge foundries. Other silicon technologies, such as silicon germanium or BiCMOS, require the use of more specialized plants and typically use smaller wafers, which keeps costs higher and production volumes lower even when in full production. Going all-CMOS thus provides a serious design challenge, but enables the highest levels of integration (single-chip solutions) with complementary silicon components such as a baseband, media-access control, high-performance I/O, memory, as well as other technology protocols and functions. The concern that surrounds implementing high-speed wireless technologies in standard CMOS is the analog front end. Performance results of CMOS vs. SiGe implementations are quite comparable. CMOS has a similar Ft (the unity-gain frequency) and equally supports fully integrated synthesizers with the appropriate phase noise. The requirements of synthesizers for time-frequency interleaved OFDM systems have been studied extensively by the Multiband OFDM Alliance. That alliance is the source of one of the two ultrawideband (UWB) proposals currently before the IEEE 802.15.3a standards group, which is ironing out a high-rate, low-power standard for short-range wireless communications. This multiband orthogonal frequency-division multiplexing (MB-OFDM) proposal uses well-established OFDM techniques employing quadrature phase-shift keying (QPSK) modulation. The mandatory mode of the MB-OFDM specification operates between 3 and 5 GHz, with optional modes that extend to 10.6 GHz. With the wide bandwidth comes the focus on the analog front end — and the synthesizers. The requirements on the synthesizers are dominated by the need to maintain robust input-jitter suppression — since UWB systems operate in noisy clock domains — and to minimize intercarrier interference inside the symbol. Studies indicate the integrated phase noise needs to be less than 2°, implying that the use of a relatively benign QPSK modulation scheme does not offer much relief. However, measurements show this is achievable with less than 25 milliwatts of power in advanced CMOS. Studies show an optimal bandwidth of around 200 kHz can be chosen to reconcile the conflicting demands of input jitter and voltage-controlled oscillator (VCO) phase-noise suppression in 130-nanometer CMOS synthesizers. The phase noise of CMOS VCOs themselves is no longer a concern, and measurements at Intel confirm that they surpass several published SiGe-based results.  | Using appropriate design techniques and optimizations an ultrawideband multiband-OFDM analog front end can be implemented in low-cost standard CMOS.
Source: Staccato Communications | Both SiGe and CMOS implementations support UWB power amplifiers at equal efficiency levels, but CMOS pays a potential penalty by requiring a slightly higher noise figure and consuming more power for the remaining RF circuits. Because the MB-OFDM specification pushes the complexity into the digital domain, the analog portion is kept to a small die area and the performance difference between CMOS and SiGe is a wash. Taking a closer look, it is clear that a 7-dB receiver noise figure (NF) is the bare minimum that will be required in the 3- to 5-GHz band, with an acceptable level of degradation in the NF in the higher bands. Since the NF is largely determined by the low-noise amplifier, which in turn is gated by the capabilities of the process technology, the noise performance of CMOS devices is a key determinant. Measurements conducted at Intel in 130- and 90-nm technologies confirm that the device performance is more than adequate to meet the demands of UWB. In fact, the data indicates that a 1-dB device with NFmin performance at frequencies nearing 10 GHz is achievable with ~10 milliamps of device current. More significantly, the NFmin is relatively insensitive to bias current, a fact that bodes well for high-volume manufacturing. This performance is equal to if not better than higher-cost SiGe devices. As we proceed down the signal chain, the baseband filter emerges as a key consideration; minimizing the filter power drain while maximizing linearity is of paramount importance. Baseband filters do not benefit from CMOS scaling trends and in fact often suffer linearity degradation due to decreasing power supplies. However, studies have shown that by combining thin- and thick-oxide devices that are now available on all CMOS mixed-signal processes we can achieve the required linearity with a power drain in the tens of milliwatts. Power-hungry converters The most power-hungry component in the receiver is the analog-to-digital converter, owing to the large (375-MHz) bandwidths involved. System studies indicate that 4 bits are sufficient to meet the demodulation requirements. Flash A/Ds are an obvious choice for this application and scaled CMOS technologies are ideally suited for these devices. We estimate that a 4-bit, 1-Gsample/s A/D in 90-nm CMOS can be realized at less than 60 mW. The receiver chain power in continuous mode is likely to be less than 200 mW. The challenge in the transmitter is delivering the time-interleaved carrier and the 0-dBM power output efficiently. Using a combination of the synthesizer and other delay-lock loop techniques, we estimate that the time-interleaved transmit chain in 90-nm CMOS will consume less than 100 mW. High levels of integration define single-chip solutions, and because the MB-OFDM specification relies heavily on digital circuitry, design teams need to select semiconductor processes that are capable of handling computationally intensive circuits. It does not make sense to implement such circuits in anything but CMOS because the geometries of SiGe-BiCMOS lag significantly behind standard CMOS processes. The implications for SiGe would mean increased die area due to the number of gates, slower switching speeds and higher power consumption of the digital circuits, resulting in poorer performance. In a system where 70 percent of power consumption is in the digital, this becomes prohibitive. Recapping the technical points relating to power, it is likely that SiGe uses less power to achieve more gain at higher frequencies in analog. CMOS uses more power to achieve the required gain at high frequencies, but because the MB-OFDM specification has minimal complexity in the RF front end, with the majority of system complexity residing in the computationally intensive baseband where SiGe uses more, the net power impact is fairly insignificant. The cost implications in support of all-CMOS solutions really make the case as to why mass markets require standard CMOS. A compromise would be a chip set that comprises SiGe front end and CMOS digital chip. Such a combination not only results in higher costs than a single-chip CMOS solution, but may also introduce technical complications, such as timing violations, noise induced by interchip routing and voltage irregularities. Dan Meacham (dan@staccatocommunications.com) is co-founder and vice president of engineering at Staccato Communications (San Diego). Krishnamurthy Soumyanath (Krishnamurthy.soumyanath@intel.com) is a senior principal engineer and the director of the communications circuit lab in Intel's Corporate Technology Group (Hillsboro, Ore.). | 
