| As technologies scale, on-chip structures shrink in size and increase in frequency, leading to rapid growth in on-chip bandwidth. But off-chip structures lack similar improvements in size and speed, creating a gap between on-chip and off-chip bandwidth and a performance bottleneck. Today, off-chip wires require a pitch on the order of 100 microns and off-chip ball bonds require a pitch on the order of 150 microns. By contrast, the pitch required by on-chip wires is on the order of only 1 micron. To bridge this gap between on-chip and off-chip bandwidth, designers can increase chip sizes both to exploit integration and to gain more input/output (I/O) pads. However, this leads to a much lower yield and greater design complexity, hence disproportionately higher cost. The development of an I/O technology that can scale with on-chip feature sizes would deliver an I/O density advantage over area ball bonds. Proximity Communication is an implementation of such a scalable I/O technology that uses the lithographic pitch of on-chip wires. Comparing its I/O density to aggressive predictions for area ball bonds shows a density improvement of about two orders of magnitude. Rather than communicate through conductive wire bonds or solder balls, Proximity Communication can push two chips together so that their top-layer dielectric and passivation surfaces touch or nearly touch. Such chips placed face-to-face in close proximity can communicate via capacitive coupling if suitable transmitting and receiving plates overlap. Each chip has transmitter and receiver circuits built using on-chip structures whose sizes scale with technology. The two chips communicate by capacitive coupling, in which transmitters drive a plate of metal on one chip that couples to a corresponding plate of metal on the other. This plate in turn drives receivers on the second chip. The face-to-face placement allows the capacitively coupled plates to be very close to each other and the transmitter and receiver structures to be small, reducing parasitic capacitance and saving power. Because the plates lie under the passivation layer, they are protected from electrostatic discharge (ESD) events. They can therefore omit ESD protection devices and further reduce capacitance and power consumption. Proximity Communication can use capacitive coupling, or alternate methods such as inductive coupling or optical transmission. The lineup
Unfortunately, communicating between chips through tiny coupling capacitors requires precisely positioned chips, and even with very careful mechanical assembly the chips will still have some residual misalignment of delta x and delta y. Misalignment by half of the receiver plate pitch will make each receiving plate span two transmitting plates, destroying the received signal. To achieve satisfactory communication, mechanical alignment must therefore occur in two dimensions. Such accurate alignment may be difficult to achieve and to maintain under thermal expansion and mechanical vibration. To reduce the need for accurate alignment, we have built an electronic alignment structure into our chip. Instead of using a single transmitting plate for each circuit, each transmitting plate is broken up into 16 so-called microplates that together occupy the area opposite a single receiving plate. Switching circuits built into the transmitting array permit one chip to transmit its signals on whatever microplates happen to align with the receiving plates, thus compensating for mechanical misalignment between the two arrays. Each microplate can get data from one of four sources on its left or right, and top or bottom. Control signals set the multiplexers to choose which data appears on each microplate. Each microplate must be able to transmit the value from any of the four nominal bit positions closest to it. Compensating for greater misalignments requires merely a full bit-shift operation before the transmit or after the receive pad arrays. The transmit array is about 400 x 400 microns and consists of 1,024 microplates. The receive array is about 200 x 200 microns in size and consists of 16 plates. In our 0.35-micron test chip P1 was 50 microns; hence P2 was 12.5 microns. In finer line-fabrication technologies the pad density should improve by over an order of magnitude. Reducing misalignment
By selecting the proper microplates to use for each transmitting location, we compensate for misalignment down to one-half of the microplate pitch, reducing residual misalignment to at most 6.25 microns over a range of 100 microns. We have tested transmission of data through the steering array, sending random bit patterns simultaneously on the 16 channels. In a 0.35-micron technology the experimental chip communicated at 1.35 Gbits/second per channel with a bit error rate of less than 1-10. Power can be brought into a chip by standard solder balls or wire bonds, but these hamper chip replacement. Other methods for power delivery include micro-springs, fuzz buttons or capacitive or inductive coupling. Those four methods would permit chip replacements and the latter two would permit a system comprising completely passivated chips. Due to wire delays, power budgets, transistor leakage and fabrication and testing costs, future scaling may fail to provide further dramatic increases in chip performance. If so, 3-D packaging may become increasingly important to increase volumetric density and reduce wire lengths. However, permanent bonding methods to produce 3-D chip stacks suffer from the known-good-die problem, preventing permanent attachment of hundreds of chips. Hence a felicitous packaging approach may interconnect yieldable 3-D chip stacks with Proximity Communication. Proximity Communication is preferable to communication over wires for several reasons. First, placing the chips close together completes as many parallel communication paths as are built into the chips without the need for wires. Second, because the communication path has low capacitance, each communication circuit operates at very low power. In addition, the capacitive coupling operates through the glass overcoating, obviating the need for static-discharge structures. And finally, the density of communication paths greatly exceeds that available with wired conductive paths such as ball bonds. Mechanically aligning chips for Proximity Communication presents some challenges that are partially overcome using our electronic alignment technique. Thus far we have received encouraging experimental results from a test chip that implements both Proximity Communication and electronic alignment correction. Robert J. Drost (Robert.Drost@sun.com) is principal research scientist at Sun Microsystems Research Laboratories (Mountain View, Calif.).  See related chart | 
