| As PCI Express becomes mainstream, IDMs and fabless companies face a new breed of test challenges requiring new production test strategies. Characterization efforts will help determine what tests need to be carried into the production phase, but companies must also consider anticipated test costs-a critical factor in any viable test strategy. To capitalize on this competitive market, they need to determine how to rapidly implement a cost-effective test strategy, for test requirements that have historically required high-cost, high-accuracy instrumentation. The characterization phase of a PCI Express device will be focused on the performance of the serializer/deserializer (serdes) I/O. Some of the instrumentation used in this phase, however, may not have the appropriate level of scalability to meet high-volume, production-test cost targets. Further, some characterization solutions will be unable to test other sectors or blocks of the PCI Express device. To do this, the following areas should be considered and prioritized. The PCI-SIG document outlines 31 tests, of which 14 have been identified as lead indicators of silicon-level performance. Further, LTX has identified three additional tests, based on significant datacom test experience, that should be included in any test list. The purpose of these tests is to enable full monitoring of the jitter content on the TX pins; provide max/min limits testing, to stress the sensitivity of the Rx pins to voltage and jitter extremes; identify the voltage characteristics of the differential signals; and enable lane-to-lane timing. Analysis will help determine how much of the above can be completed using loopback techniques. But it must be feasible to enable independent monitoring of Tx and Rx pins in production to determine the root cause of any yield dropout. As well as the serdes-oriented tests, all PCI Express I and O pins will require such tests as dc parametrics, receiving and driving of scan vectors and parallel digital vectors. Ideally, all capabilities can be switched within the ATE itself. Integration
To support the nonserdes pins on the device, any manufacturing test solution must support the functionality of the rest of the device-for example, high-speed, synchronous bus architectures running up to and beyond 1 Gbit/second. These features must be fully integrated with any serdes test capability. The test platform must have the architecture and instrumentation flexibility to support characterization and a fast track to production. This includes having a universal pin structure that enables switching of dc features, scan data, digital data, pseudorandom binary sequence data sequences, jitter injection, time-domain waveform analysis, loopback modes to enable device Tx to Rx connections and high-bandwidth connection to TIA resources. The platform must allow test resources to be cost-effectively scaled to enable multisite testing, and test options must support multiparallel and parallel multilane testing. By integrating all the required functionality behind the universal pin structure load board, designs become more scalable. The test platform must also offer a software environment that enables the addition and removal of test blocks to meet turn on/turn off requirements. Further, the test environment must provide a range of tools that simplify debugging and analyzing the multitime, multifunction applications, as well as data collection and analysis tools that aid in the task of yield monitoring and improvement. As can be seen from the above, serdes testing is just one component of the overall test requirements for an effective production-test strategy for PCI Express devices. By taking into account all of the items discussed above, device quality can be ensured and optimum test economics can be achieved. Steve Wigley is vice president of product marketing for LTX Corp. (San Jose, Calif.) and Ian Harrison, pictured above, is the company's senior director of applications, based in Westwood, Mass. | 
