| Chip designers may question the hype over design reuse, insisting they've been reusing code for years. Probe a little deeper, and this reuse consists of taking a similar block and using it as a starting point or example for the next-generation design. While using existing designs to get a running start may be an admirable practice, it is hardly reuse. The original design is tweaked, enhanced, and it's the rare designer who can resist putting his or her own spin on the implementation. Some of the code may be recycled into something recognizable from the original design, but the end result does not approach the benefits that can be derived from black-box reuse. Even relatively minor changes to a design can dramatically increase the risk when integrating the design into a system-on-chip. Seemingly innocuous modifications may have an impact on an unintended portion of the design and will likely not be caught unless a comprehensive verification suite is completely run. The ultimate goal of design reuse is to integrate a "known good" piece of intellectual property (IP) and verify the interfaces in the SoC. With that said, how do you "know" a design is good? The quality of a design can be measured by using the Quality IP (QIP) Metric from the Virtual Socket Interface Alliance. The premise is that good designs are a product of good design practices from IP conception through customer delivery and support. QIP details the considerations that the design team must meet during development, as well as what the end user needs to ensure integration and reuse of the IP without any changes. To attain black-box reuse, the IP must start with detailed system requirements, from which a solid design specification is derived. The system requirements should be cross-referenced to the design and verification specifications. It is important to keep the potential system targets in mind when specifying and designing IP for multiple black-box reuses. Built-in configurability helps retarget the IP to different systems without code changes. Bus widths and architectures, memory types and sizes, and even architectural implementations such as interrupt controllers can be configurable. The portability and savings realized when integrating the IP in multiple systems more than make up for the additional overhead of the initial verification effort. Coding counts
The constructs and coding styles used also contribute to the reusability of the IP. For example, combinational feedback loops will make the use of formal verification tools and cycle-based simulators much more difficult. Obviously, the handling of clocks and resets can have a huge impact when the IP is integrated into the SoC. The IP state, including the direction of bidirectional pins and the state of logic in multiple clock domains, must be predictable during and after reset. Any required clock gating or generated clocks should be separately partitioned to ease the SoC design-for-test strategy and implementation. Verification is arguably the single most important element in ensuring that IP can be reused in a black-box fashion. The QIP metric tracks and quantifies coverage and adherence to the specification for VC/SoC functional verification from VSIA. This specification details standalone IP verification as well as verification of an IP block within the context of the SoC. The verification environment comprises testbenches, models, scripts and other deliverables and the specification details best practices for their development and implementation. It also details the handling of clocks. Of primary interest to end users is how to actually integrate and use the IP, without having in-depth knowledge of the code. Detailed integration, hardware and programmer reference manuals, as well as errata or release notes, are invaluable. The QIP metric quantifies this information, as well as the end-user perspective on the reusability of the IP. These concepts are applicable to all IP, whether internally or externally developed. For purchasing third-party IP, however, the QIP also measures the quality of the supplier. It looks at the support and maintenance models, as well as training and internal corporate quality factors. Kathy Werner (kwerner@vsi.org) chairs the VSIA IP Quality Pillar and is reuse manager at Freescale Semiconductor Inc. (Austin, Texas).  | See related chart
The quality of an IP design can be measured by using the Quality IP (QIP) Metric, the premise of which is that good designs are a product of good design practices. The IP Maturity and Vendor Assessment, which is part of the QIP, measures the quality of the supplier.
Source: VSIA | | 
