Is IP Quality Achievable, Measurable and Enforceable through the Design Chain?

by Saverio Fazzari, Cadence Design Systems, Columbia, MD USA
and Dan Moritz, Virage Logic Corporation, Burnsville, MN USA    

Abstract:

The modern design chain for System-on-Chip (SoC) development is growing to include a larger number of suppliers.    Some parts of the design, as well as various steps in the creation of the SoC, are done by different organizations. The SoC design team must manage the flow of data between the various sources. Companies must measure the cost of internal creation versus  procurement for all aspects of the design development, and individual sections, since the financial aspect is critical in today's competitive market.  The functional blocks, or intellectual property (IP), that make up the design must be carefully selected for success.  This is done by considering various factors.

Many individual companies and consumers have tried to put together guidelines to identify quality IP.  In the last few years, there have been concentrated industry efforts to put together complete solutions, such as the VSIA Quality IP (QIP) program and the Fabless Semiconductor Association (FSA) IP subcommittee. These standards attempted to be all encompassing for different types of IP.  There are also additional IP certification programs available from individual vendors.  With so many different programs, the IP selection process becomes more difficult.. For example, with the availability of the various IP standards, both from individual companies and from the industry groups, can the issues of IP quality be addressed?  Also, how should the information be shared with the consumer about the IP?  The major difficulty is determining how to use the data from the various standards effectively.

Both the IP consumer and the IP provider are faced with a classic challenge.  The consumer needs to have confidence in the IP choices available.   The provider should qualify their IP in a way that makes consumers more confident about their decision.  This paper will demonstrate, with design examples, the merits of the various standards and how they can be used in making efficient IP choices.

IP and SoC Design Today

IP are key functional blocks used in the implementation and verification of the SoC design.  They vary in complexity from the cell libraries of the target technology to the model for a complex processor or an interface protocol such as PCI-Express.  Today’s designs include many different types of IP that must operate together according to the project’s specification.  There are also IP blocks in the test environment used to validate the behavior of the system.  A completed SoC example would be any multifunctional electronic device, such as a cell phone or PDA that has additional capabilities built-in such as camera features. Cost, performance and feature targets drive the market window for development of any SoC.  Commercially available IP can significantly speed up development time of a SoC; however, this IP should be of high quality and offer little to no risk during the actual design process.

The need for IP has led to growth in the external IP provider industry. The SoC design teams typically cannot develop all of the required IP blocks internally because of time, expertise and budget constraints.  They must look to other suppliers and determine if the external IP will work correctly in the design. The selection of IP by the design team is critical, as an incorrect choice could have significant impact to the project’s cost or availability during the market window.  Design teams now look both internally and externally for IP that can be used easily in the design.  

The use of IP in electronic design has led to two emerging focus areas: system integration and validation.   So much capability is incorporated into individual SoC designs that the amount of system testing needed has increased significantly.   The availability of IP blocks from other sources allows SoC design teams to focus on their core competency and system-level issues.   



 
Boring down into nitty-gritty of implementations [sic] Ron Wilson, EETimes August 23, 2004.

This survey from EEtimes, highlights the use of IP in new designs. IP availability allows new startup companies to compete against larger well-established companies.   These smaller organizations can leverage experience and technology from other companies to meet a market target and timing window.  In this scenario, it is important to have the IP flowing freely so that the design team can leverage the technology from all of the possible design chain providers, both internal and external.   With this reliance on third-party IP, the question of quality becomes more critical.  Typically, 70% of the SoC under development may consist of IP blocks that were developed outside the scope of the project.  A critical question for the design team becomes, “How do you determine the IP’s effect on the project, either from a negative or positive perspective?”

IP Selection
 
There are many different variables that consumers use to make their choices of  IP.   There are business, technical and support issues that will vary from customer to customer.   Factors such as cost models, support, customization, IP model features and tests should be considered.   Customers typically weigh all of these factors differently.   It is critical that there is a way to measure and demonstrate the quality of the IP. A vehicle is needed to compare different IP blocks. It is a unique problem for emerging and recently solidified standards such as PCI-Express.  For example, in the last 12 months, many companies trying to get products to market needed access to a PCI-Express model.  The companies would go through multiple IP vendors to find a good quality product or else create it themselves.  There is not much history of the PCI-Express IP with customer references available or quality measurements to help make the decision which was often  left to politics, price and emotion.

There is a lot of debate in the industry regarding how to analyze, measure, quantify, standardize and enforce both the quality and interoperability of IP components, making selection of the appropriate IP difficult.   Everyone would like to see better ways to ensure that the quality of commercially available IP is improved. There has also been a great deal of research and discussion on ways to have industry standards help with the IP selection process.  This problem has been addressed in many different ways. Some companies have promoted methodologies for quality that work within their environment.  A third-party IP vendor must be certified at each company they want to sell to .  There have been other approaches focusing on different solutions that may dominate a particular aspect of the design flow, such as logic synthesis.  These limitations prevent high quality IP from being available to the customer.

A big problem in the third-party IP industry is product quality.  The perception many designers have of IP products is that there are several offerings, but none of them are complete.  An offering in this case is a reusable block of code that has been fully tested and verified.  Many companies that provide design services want to sell their project code as an IP block.   Customers also might have incorrect expectations about the capabilities of the IP.  Some people expect the software IP to be able to guarantee that the final product will achieve particular hardware compliance. Explicit understanding of scope is required to reduce risk.

 The bottleneck to growing the third-party IP business primarily revolves around IP quality and interoperability.  The designs that are being built require integration of multiple IP blocks in the design and additional pieces into the system verification environment.  For example, a customer might be designing with a Tensilica processor along with Virage Logic memory IP  using Cadence tools targeting a TSMC foundry process.  The quality of all of the IP is critical to all members of the design chain since poor IP will reflect back on each of the different suppliers where the customer has to determine the cause of any problem that might arise. For example,  Cadence might receive  a customer issue associated with a particular configuration of IP and their tools.  The steps to resolve the issues first start with determining which part of the configuration has an issue.  All the design chain members must be able to work together to resolve the issues.  

Some customers have had negative experiences using third-party IP.  Reasons for this may include incomplete models, lack of support and/or incompatibility with the design flow.  In many cases, customers want to see a solid list of references of previous users of the IP block.    Access to source code is another deliverable that people ask for.  In some cases, customers modify the IP and then ask for support when their changes do not work.  It is important to make this process clear, easy and more manageable.

Design Chain Impact

In order to provide confidence to the IP user, it is important for the IP provider to demonstrate that they have the capability to deliver a high quality product. Partnerships between all of the various design chain suppliers are critical to be successful in using IP.  Currently, the common expectation is that something will go wrong with third-party IP, and there needs to be an effective resolution path. Many consumers are looking at models that protect them, since third-party IP can be very volatile.  The environment that the IP was developed in may not reflect the IP user’s environment.   When IP is chosen, the user would like to have confidence that it will work well for them through the design flow.  A worst-case scenario is that IP suppliers and EDA vendors are engaged in finger-pointing for the source of the problem .  Each member of the design chain has various functionality and reliability metrics to identify the right IP.   

It is important to determine what partners can provide to help in qualifying the IP choices. Individual metrics for companies can enhance the selection process.  Each company can provide a “:value add” in particular areas which make them unique.  For example:

• Foundries like TSMC can provide manufacturability information about IP in a particular process
• EDA vendors such as Cadence can show how well IP fits into their various tool platforms
• Companies like Tensilica provide design platforms for their processor offering that allows for more effective software integration and hardware development
• IP providers like Virage Logic can give information about the core IP cell libraries and models that impact the system’s overall performance and timing characteristics

Many companies do this kind of testing because it is important to identify the potential solutions that make use of their respective products more effectively.  The need to integrate IP outside of their direct control is a natural occurrence in SoC design today.  The convergence of many different types of IP working with design tools must be clean to allow projects to be completed on time.  Savvy customers are looking to see what kind of relationships exist between the design chain suppliers to help minimize risk.  If it is clear that companies have been working together on many fronts, the chances are that their product will work as expected. This partnership gives confidence to the consumer that all of the various companies will provide seamless support.

Quality Metric Approaches

Virage Logic, as a supplier of logic, memory, and I/O IP, has developed a multi-faceted and layered approach for ensuring quality and compliance with VSIA QIP, foundry, and individual customer requirements.  IP developers create checks for use during the development process.  Unit testing occurs within each product group, which measures compliance with company-wide design and modeling goals.  Finally, an integration test is performed to ensure each Virage Logic IP module works with the others.  

A variety of checks are performed at each level, but they broadly encompass 6 key areas:

• Library Construction Checks – Use internal software to ensure each EDA view matches the original design database.
• Library View Cross-checking – Uses EDA tools that load multiple views to ensure consistency, i.e. SoC Encounter™ uses Liberty and LEF. If there are any discrepancies between the model, the tool reports an error.
• Tool versus Golden Data Checks – Compare the results of an EDA tool run with a golden accuracy tool. For example, SignalStorm versus SPICE for accuracy.
• Tool versus Tool Checks – Compare various EDA tools with similar functionality and identical model inputs to ensure consistency throughout the flows.
• Methodology Checks – Creates several typical design flows and validates the library’s operation at each point to simulate actual usage.
• Hardware testing – Confirmation of designs using test chips at each foundry.

These checks work together to ensure that the design intent is communicated properly to each EDA tool and that all views work quickly, accurately and consistently throughout the methodology.  These checks were developed in partnership with several foundries, EDA companies, and Virage Logic customers in order to satisfy the broadest possible requirement set in the most efficient way.  QA reports and QIP scores provide customers with a starting point in selecting the right IP with the lowest risk.

Industry organizations are trying to address this IP selection need through the creation of tools to assist in the evaluation.   VSIA has put together a checklist to grade IP in determining its quality called VSIA QIP. It was developed with input from a large number of companies including EDA vendors, IP providers, consumers and manufacturers.  These companies provided input based on internally developed standards that were then merged into a full design checklist to address any issues.  The checklist is then completed by the IP provider and the IP customer can complete a part to determine the quality of the IP using a scoring system to rate the various questions.  The example below shows a QIP question.  These are rated in various categories so critical issues are weighted more heavily in the scoring system.

Are synthesis scripts with timing constraints provided?	y/n	Imperative
Are scan insertion scripts provided?	y/n	Rule
Is the order of file compilation clearly documented?	y/n	Rule
Does the IP include a MAKE file or other means of installation or compilation?	y/n	Guideline
Does the IP have a documented and well ordered directory structure?	y/n	Rule

This QIP has been used by customers to help identify key issues in using IP for projects.  It is difficult to handle the different situations when creating standards.  Questions in the standard are created with arbitrary answers that attempt to classify the strictness of each requirement.  This can hide the information that may be needed by the decision maker.   It is important to enable innovation in the process.  

VSIA QIP is a first step in driving the process for selection, but should be augmented.  Information about what EDA tools were used to create or test the various views that are provided should be available because the IP user needs to compare this against their EDA environment.
Cadence has the OpenChoice program that is designed to promote Cadence’s compliant IP solutions.   Cadence’s focus is to identify and qualify IP to promote the blocks that work well in Cadence tools.  This will provide Cadence tool users with information about partners who have worked with Cadence to provide verification.  There is an in-depth certification process that the IP vendor and IP must go through.  It leverages standards such as VSIA QIP to do the IP analysis.  Additional questions and steps have been added to test the integration with Cadence tools.  

There are additional audit steps that are performed in evaluating the company’s processes and methodology.  These steps encompass evaluation of the development process used by the IP provider.  Cadence provides IP development guides for partners to take advantage of Cadence tool features.

Quality Lessons and the Real World:

Quality is an admirable goal to achieve.  The project development team wants to be able to minimize risk with this critical IP choice.  The design chain providers want to promote the right IP to make it easy for their users to provide the tools.  The IP provider wants to make sure that the customer can clearly see the differentiation between their product and others.  Today these goals are hard to achieve.

The standards promoted by the industry rely on the users and provider filling out the information correctly.  There is no independent organization to review the results.  The data may show that the IP is functionally correct, but how does it work in the context of the system or environment? The company standards also reflect the IP usage in a particular context.

 In a number of internal projects at Cadence, the Design Services team evaluated some third-party IP for use in various engagements.  The goal was to ensure that the block could work within the Cadence environment and meet the functional requirements for usage.  Over 50% of the IP blocks did not meet the goal.  This means that the IP was not made to work in the time frame needed by the design team.  Many of the issues had to do with EDA view issues.   The version of LEF that the IP was developed with was not compatible with the Cadence tool.

At Virage Logic, customers often take advantage of customization options that leverage emerging EDA tool capabilities and unique design/modeling requirements that differentiate their products.  These are contractually explicit, but modeling decisions can produce unexpected results. In some cases, delay numbers in the EDA tools should be skewed conservative instead of centered.  If the consumer did not specify this during negotiation or understand the IP development process employed, the risk for successful implementation of the IP rises.  Knowing the right questions to ask can reduce risk. This is a role for IP standards to provide a common set of questions.

It is important to be cognizant of the information that is available to the IP consumer and leverage it appropriately.  Many sources exist for finding qualified IP lists.  The major EDA tools and IP technology providers can help set the context of what to look for.  For example, awareness of the EDA tool version supported in your flow.  Make sure that the IP vendors can support this requirement or that the EDA vendor can show there will not be issues.  Find out what version of the EDA tools the IP was tested with and make sure that this did not have significant changes with your environment.  Make sure that all the right EDA views are available.  Many times IP vendors may not be aware of what is needed.  Evaluate the process by which the IP is developed and validated.  It needs to be a delivered, reusable product.  Finally, do the IP providers have a partner relationship with other key providers in your flow such as the tool provider?  This gives insight into how effective their IP might be and leveraging the EDA tools capabilities.  In summary, the key information requirements for success are:

• Version information of the EDA tools tested against
• A complete list of EDA view versions available
• Process documentation for how the IP is developed, make sure the IP is constructed properly
• Partnership agreements to ensure the IP vendor already works with your other design chain members

These actions can help clarify existing IP quality. Much of this IP information is available through the work that is done by companies such as Cadence and Virage Logic.

Conclusion:
 
Identifying quality IP is a critical part of the modern design progress.  It is clear to the user that poor IP can have a substantial impact on the success or failure of the project.  When selecting IP, it is possible to achieve the goal of finding the right IP by looking to the key parts of the development process.  It is important to find companies that work well together so that the basic pieces such as libraries and EDA tools are integrated.  All these companies have information about IP that has worked with their technologies.  Leveraging all this information can enable a more efficient process of selection that maximizes the return on the cost of evaluation.  As long as there is communication and clear commitments to a rigorous process, the ability to choose good quality IP is achievable.

Saverio Fazzari is the Technical Marketing Director responsible for compliance testing in the Cadence OpenChoice IP program.

Dan Moritz is the QA Program Manager for Virage Logic Corporation’s Logic and I/O products.