Apr. 04, 2019 - Process technology and verification enjoy a circular and mutually beneficial symbiotic relationship. Improvements in functional verification tools make technology adoption economically viable, and technology advances spawn more complex designs, which demand an increase in sophisticated verification. ...

Mar. 25, 2019 - The intent of this paper is to explain the varied kinds of DRCs (Design Rule Checks) that are encountered in the Physical Design flow. This paper will discuss the Metal DRC violations (7nm Technology) generally seen at the block level and outline the practical approach to fix them.

Nov. 29, 2018 - This white paper proposes an effective approach for moving vehicle classification followed up by vehicle counting, for classified types of vehicles. This data helps in strategic city planning, and in generating meaningful insights for improving efficiency and reliability in Traffic Management.

Apr. 18, 2018 - Near threshold design is delivering improved battery life for demanding battery powered applications. One key challenge remains - what about the SRAM?

Jan. 15, 2018 - With the evolution of Internet of Things, the requirement for ultra-low power systems have increased. To design a low power system, we must apply all the possible low power methods at each level of the system implementation. Currently, most of the systems are designed by integrating off-the-shelf Digital ...

Nov. 27, 2017 - An electronic design that can be used in multiple ASICs/SoCs is a potential “IP” in the semiconductor industry. The premise of semiconductor IP market is simple – IP vendor focuses on designing, maintaining and updating the IP and ASIC/SoC companies focus on their differentiation, thereby fuelling ...

Jul. 03, 2017 - As the system, software & IP complexity is increasing so is the demand of SystemC models & Virtual Platform for verification. To achieve it, the key requirements are that the models/platform should be developed fast, reusable & highly accurate. We are sharing the experience of our company 3D-IP Semiconductors ...

Jul. 03, 2017 - This paper discusses about the intelligent low power techniques such as context based clock gating and how they are useful for IoT applications. It also describes how it improves the overall power efficiency of the system. The power statistics shared shows how the overall idle power and functional power ...

Jun. 26, 2017 - Verification is an integral part of any integrated circuit development process. The verification process must establish that the design meets its specified yield and performance criteria over the full range of operating conditions before tape-out sign-off. The process generally involves taking abstractions ...

May. 15, 2017 - The Accellera Portable Stimulus (PS) standard is expected to be released early this year and that will set the stage for the abstraction of verification to be raised to the system level.

Mar. 09, 2017 - This article explains a new holistic methodology that combines analytic methodologies such as FMEDA with simulation-based methodologies to significantly reduce the safety verification effort and achieve faster product certification. Automated fault injection is a well-established test method used to ...

Mar. 06, 2017 - propose a novel method of breadcrumb insertion that is non-intrusive and easy to setup within the context of the IP-SOC development ecosystem. This method adds no overhead on the IP side nor on the SOC side. It is architected to be non-invasive but effective in dealing with today’s mix of reuse IP’s ...

Feb. 24, 2017 - This paper talks about an API- (Application Program Interface) based verification approach that can be adopted for a whole segment of ASIC applications.

Oct. 31, 2016 - In-design verification is needed to shorten design cycles and maximize circuit performance, ensuring physical designs are correct by construction. Physical verification often forces a decision between accuracy and performance for larger designs.

Oct. 10, 2016 - Achieving system-on-chip (SoC) timing closure is a major obstacle in the FinFET era. Even though designers can now use faster transistors that consume and leak less power than before, FinFET technology does not address the on-chip communications infrastructure or metal line resistance/capacitance issues ...

Sep. 13, 2016 - For many years, design verification has been the biggest challenge for any company involved in ASIC design. To address verification challenges for increasing complexity in ASIC designs, over the period of the last couple of decades, various hardware verification languages (HVLs) have emerged. Starting ...

Aug. 01, 2016 - This white paper is targeted to briefly discuss a few methodologies that can be used within the existing GBA implementation setup to extract the benefits of PBA without compromising signoff.

Jul. 04, 2016 - Innovation is the key to surviving the rapidly changing world of embedded electronics. Efficient testing is a crucial step to achieve the design of reliable products. Emerging applications be in aerospace, automotive or industrial automation systems, need to be tested thoroughly and rigorously. Consequently, ...

Jun. 13, 2016 - This paper will help to navigate through the key concepts of packet based Fronthaul and discuss the implications of the adoption of latest Time-Sensitive-Network (TSN) IEEE 802.1CM standard, the IEEE P1904.3 Radio over Ethernet (RoE) standard and latest Next Generation Fronthaul Interface, (NGFI) IEEE ...

Mar. 21, 2016 - Constrained random verification is a standard industry approach to test digital intellectual properties. Currently used randomization methods do not guarantee unique testcase with different randomization seeds and reproducibility of scenarios if testbench is changing. Moreover, control over exhaustibility ...

Feb. 15, 2016 - Due to the lack of thorough specifications to assess the performance of voice detection solutions, it is a real conundrum for users to evaluate the best solution among a jungle of true and false detection claims and without any benchmark. ?The aim of this article is to help IP procurement managers, ...

Jan. 11, 2016 - IPs (Building blocks of ASIC/SoC e.g. CPU, GPU) build and sign off in a wider sense. It doesn’t always mean Chip Timing, Design Rule Constraints & Power Closure of a block, but also refers to the creation of a layout/partition around the delivered build/sign off IPs/blocks. This would further refer ...

Dec. 14, 2015 - In this article, we will focus on metal ECO implementation methodologies with emphasis on mask programmable cells.

Nov. 23, 2015 - This white paper outlines the key requirements for ISO 26262 certification and demonstrates how to accelerate the development of safety-critical IP and SoCs through the use of out-of-the-box safety-ready IP with advanced verification qualification tools and methodologies.

Oct. 19, 2015 - This paper will interpret multiport S-parameters for several memory interposer design cases. This will help the audience understand some of the performance characteristics that can be inferred from the S-parameters, as well as some of the interactions between the interposer and the device under test ...

Oct. 05, 2015 - This article will describe how easy it is to create efficient self-checking tests that are straightforward, and reusable during gate level simulations. It is surprising that, by changing the data flow, we can have benefits for the test bench, reducing the complexity of scoreboards, which also means ...

Sep. 07, 2015 - This white paper outlines the HDMI IP certification flow from internal quality, functionality and interoperability testing to certification of the latest HDMI Compliance Test Specification (CTS) at an Authorized Test Center (ATC).

Jul. 30, 2015 - The PCIe standard has become a popular choice for high-speed serial communication but as successive generations of the standard offer increased data rates, reference clock performance is becoming progressively more critical and the specifications more aggressive to ensure good timing margins.

Jun. 29, 2015 - In this paper we have discussed about the typical .c/cpp building flow in complex SoCs.In this paper different stages in C/CPP building flow are mentioned and how the stimulus is generated(corresponding to what is in .c/cpp) to modules and how the core takes the stimulus to module i.e. how core/processors ...

Jun. 24, 2015 - Using a feature-rich implementation tool helps designers focus on their own product differentiation while accelerating time to market and meeting cost targets.

Jun. 15, 2015 - This paper discusses the models and methodology that are used commonly for characterizing the timing parameters of various sequential logic cells which are key elements of synchronous design.

Jun. 08, 2015 - This paper discusses about the requirement for backdoor loading and comparison of processed data (in digital verification environment) and explains a method to implement such a scheme, which saves a lot of simulation time, while maintaining the data integrity.

Jun. 05, 2015 - One of the major issues faced in the verification of analog or AMS IP in the SOC environment is the behavioral model’s limitations. Since behavioral models are not perfectly able to replicate analog behavior in a verification environment, many critical bugs are left uncovered.

Apr. 20, 2015 - Technology scaling and process evolution is the most prominent nature of VLSI/ULSI industry. Following the Moore’s law and the advancements in both fabrication process and characterization the VLSI market provides a wide range of standard cell models and libraries to be used for design implementation ...

Apr. 06, 2015 - This paper describes a CSoC platform and configurable digital subsystem IP which can be deployed for development of IOT edge devices. The paper encompasses the different attributes of IOT edge device that can cater multiple industry segments, key features and benefits of CSoC platform, components of ...

Mar. 30, 2015 - In this paper we will see how the flash memories developed using Carbon Model Studio helps to bring up an ARM® Cortex A7 flash memory sub-system with primary and secondary boot codes. Flash memories system demonstrated here can be used for early boot code and driver development for any CPU based SoC. ...

Feb. 09, 2015 - One reason that the power-of-two FFT dominates the landscape of high performance real-time signal processing applications is the perception that alternative non-power-of-two (NP2) circuits are difficult to implement.

Dec. 15, 2014 - When implementing new embedded applications, industrial companies are facing new challenges: these applications are very complex to program (between 5 and 10 million lines of code are common) and require handling of several possibly heterogeneous models and languages. Integration choices are wide-ranging, ...

Oct. 13, 2014 - In this paper, power, area performance parameters of 8-bit pipelined asynchronous processor is measured and compared over similar feature synchronous processor. The Asynchronous processor supports 28 Arithmetic and Logical Instructions.

Aug. 28, 2014 - There are several clock jitter types, measurement methodologies, and corresponding specifications. But most hardware designers don’t have the time to research these, and the detailed nuances of clock jitter specifications can seem like trivial minutia to the board designer.