Jan. 03, 2012 - An Anonymous post on the Verification Guild commented “Without first-rate verification engineers, most of the industry will be shipping second-rate designs. Where's the glory in that?” This nicely summarizes the semiconductor industry’s need for skilled hardware verification engineers.

Dec. 12, 2011 - This paper documents work that has been carried out to automate the checking of system software architecture specifications of SoCs. Checking the architecture manually can be time consuming and prone to error. This is especially true on architectures that are large and complex. To achieve automation ...

Oct. 15, 2012 - Based on the assertions approach, this paper presents an innovative methodology for the verification of analog and mixed-signal circuits which embeds detectors at each step of the hierarchical verification process to increase Quality Control and reduce Time to Market. This paper illustrates the approach ...

Oct. 05, 2011 - Static-timing analysis is a key task during chip design that directly impacts design cycle time. Hierarchical techniques are used to break down design complexity into manageable units...

Aug. 29, 2011 - This paper presents two unique solutions for facilitating functional coverage in VHDL and SystemC. One approach is to use post-simulation Value Change Dump (VCD) files to calculate functional coverage. The other approach, which is applicable only to SystemC, proposes extending the SystemC Verification ...

Jul. 18, 2011 - This paper aims at presenting an IP core whose purpose is to perform real-time speaker verification. The IP core can be used as part of a system to check if the speaker is really the one (he or she) who claims to be.

Jun. 30, 2011 - In this product how-to article, TI’s Loc Truong describes how to use inter-processor communication and state machine design to reduce the overall system power in a heterogeneous dual-core system based on the company’s OMAP-L138 C6-Integra DSP + ARM processor running its in-house dual DSP/BIOS RTOS. ...

Jun. 20, 2011 - This paper presents two unique solutions for facilitating functional coverage in VHDL and SystemC. One approach is to use post-simulation Value Change Dump (VCD) files to calculate functional coverage. The other approach, which is applicable only to SystemC, proposes extending the SystemC Verification ...

May. 16, 2011 - This paper outlines recent a new architecture for implementing a communication channel between two highly-integrated dice. It shows how the on-chip interconnect can be extended to bridge between chips while retaining high bandwidth and low latency. In addition, the technique allows other signals to ...

Mar. 21, 2011 - Today’s on-chip Analog/Mixed-Signal and RF (A/RF) systems have reached a limit of size and complexity where transistor-level SPICE and FastSPICE simulation approaches cannot deliver a verification solution on time. Challenges include, of course, circuit size, but also the heterogeneous nature of ...

Feb. 14, 2011 - As custom designs begin to target 45nm-and-below process technologies, they have become so large and so complex that manual design methodologies that have stood the test of decades are no longer sufficient.

Feb. 02, 2011 - To assess where Electronic System Level (ESL) is today, Chad Spackman, verification technologist at Open-Silicon, looks at the past progression of design entry methods and the fundamental motivations behind the progressions.

Jan. 26, 2012 - With increasing pressure to produce semiconductor IP quickly for the SoC marketplace, design teams with limited resources are resorting to higher levels of design reuse of IP owned by other teams. A system called Quality Maturity Server (QMS) was developed to organize, record, and maintain metrics on ...

Dec. 08, 2010 - AMS circuit design requires the adoption of specific recipes, the sharing of past experiences, and a huge number of design explorations with different constraints and parameters. To speed convergence towards design quality closure, we need a methodology to turn analog design practices into formalized ...

Dec. 08, 2010 - A new approach to modem development separates the modem-specific software from the hardware and, therefore, has a profound impact on the platform design flow

Dec. 02, 2010 - For about two decades, hardware designers have been trying to use high-level synthesis (HLS) tools. The primary goal of high-level synthesis tools has been to increase design and verification productivity by raising the level of abstraction and by defining the architectures using less code. In addition, ...

Dec. 02, 2010 - This article is about Alcatel-Lucent experience in applying formal verification techniques to an ASIC design in a large communication system.

Nov. 25, 2010 - In nature, long periods of relatively stable environments are occasionally punctuated by large-scale changes that are the catalyst for evolution to create a large variety of mutations, and then for natural selection to weed out the unsuccessful ones.

Oct. 20, 2010 - These days, IC design engineers have more functionality to implement in their designs than ever before, even though design schedules are shrinking. Although design-for-test (DFT) is absolutely necessary to enable thorough and cost-effective manufacturing test, it potentially makes the overall design ...

Oct. 11, 2010 - In this paper, we present a code generation flow to deploy system applications over hardware architectures based on abstract descriptions. Our approach is defined in two steps: a front-end step which deals with abstract description of the application, the architecture (in extended IP-XACT), the mapping, ...

Oct. 04, 2010 - Many chip designers use IP to improve their productivity, but unfortunately not all IP is created equal. Ed Bard, senior director of marketing, IP, and Ralph Morgan, vice president of engineering, IP, both of Synopsys, suggest that to separate the good from the bad, design teams must exercise proper ...

Oct. 04, 2010 - There are several efforts to solve the problem of modeling FSM coverage. In this paper, we present two new methods to implement the recording of FSM coverage into the functional coverage model in a constrained random coverage-driven verification environment. These methods enable state machine coverage ...

Sep. 17, 2010 - Behavioral modeling has caught on quite fast in the analog verification community. A RTL like description on analog, RF and mixed-signal blocks has opened up more possibilities of thorough top-level verification for these cores. Now, the power and finesse of digital verification is being brought into ...

Aug. 25, 2011 - Transaction analysis and debug between multiple abstraction levels is now possible with current technology. This paper will present an API and implementation for recording transactions from SystemC, C or C++, SystemVerilog, VHDL and Verilog. Additionally, we'll discuss how to record transactions from ...

Jun. 21, 2010 - This document discusses Random constraint-based verification and explains how random verification can complement the directed verification for the generic designs. In our case this is demonstrated by an “ARM processor based platform”.

Jun. 14, 2010 - This paper focuses on the verification challenges and the methodology used to verify a low power design that embeds a combination of techniques to save power.

Jun. 07, 2010 - This paper presents work that has used the OCP-IP modeling kit[1], and shows the benefits that the kit brings.

May. 23, 2011 - In this paper we have present an optimize power aware architecture named as “Cluster Memory Architecture”. This Architecture is implemented in Design and Development of 60 fps Super Scalar IP which can convert 60 VGA Frame to Full HD Frame per second. This architecture ensures similar or reduction ...

May. 31, 2010 - In this document we introduce Duolog’s Socrates chip integration platform, a hub for standards-based IP integration. By enabling high-quality design, IP reuse and high-level integration we will show how Socrates helps to realize the EDA360 vision.

May. 10, 2010 - The increasing structural complexity and the decreasing size of integrated circuits, associated with the reduction on design time, demands that the hardware designer uses a very well planned design flow to obtain high quality IP-cores. With increasing demand on more complex IP-cores, mechanisms for ...

Apr. 04, 2011 - One of the challenges for present SoC designers is to ensure that their SoCs consume least power. Since almost all SoCs use a set of IPs, it’s important for the IP providers to give different power reduction options in their IPs, enabling the SoC designers to design a power optimized chip. This paper ...

Apr. 19, 2010 - By increasing their usability, applicability, and quality of results (QoR), high-level synthesis (HLS) solutions are proving that they can fulfill their initial promise. One day, not using HLS will be like not using RTL synthesis today. And that day will not be long. Many hardware engineers are already ...

Apr. 01, 2010 - You work in an environment where demanding design goals and aggressive project schedules go hand-in-hand with the push to get more complex products to market faster. And you have just finalized the RTL description of your company's next-generation product, a large system-on-chip (SoC). With just a few ...

Mar. 22, 2010 - This paper looks at mixed-language design integration from both the EDA tool developers’ and designers’ perspectives. It describes different approaches and provides useful insights to help users select the best option for integrating two IP blocks in a mixed-language environment. We will provide ...

Mar. 17, 2011 - The paper describes the methodology used for functional verification of the USB 3.0 device controller core. The core model has been developed at two different levels of abstraction: RTL model for synthesis and SystemC TLM model for high speed simulation, early software development and early test-bench ...

Mar. 08, 2010 - The main goal of this article is to focus on the difficulties encountered by SoC integrators when selecting an embedded microcontroller (MCU). Indeed, the selection is based on MCU performances, but the comparison can be difficult and compromised when considering all the parameters influencing these ...

Feb. 25, 2010 - This paper presents versatile software architecture for IP verification in an integrated system environment. The proposed architecture is re-usable across various IP’s and operating platforms. This software architecture speeds up the IP verification process by identifying common ground work required ...

Feb. 11, 2010 - We propose a new methodology flow which will allow the visual definition of a complex SoC through instantiation of parametric IP such as processors, SDRAM controllers, DMA engines, on-chip buses, peripherals, switch matrices and coherency directories, coprocessors, etc.

Feb. 02, 2010 - The relentless increase in the number of transistors integrated on a single chip continues to take its toll on verification teams. Market pressures squeeze product development times, leaving little room for error.

Jan. 25, 2010 - This paper will emphasize how a recipe that combines methodologies provides a superior VIP, one that reduces effort and debugging time. While avoiding reference to specific EDA tools when possible, the article also describes the creation of VIP flow at a conceptual level.