Jan. 11, 2010 - With the rising complexity of mixed-signal SoCs, designers require new approaching in solving test challenges. Mixed signal verification presents a unique challenge as the analog portion of the design requires highly accurate, and time consuming, analog simulation.

Jan. 05, 2010 - With today's design starts using 65nm design rules or smaller, the number of cores in an SoC can exceed 100. Connecting 50 or 100 cores breeds challenges that SoC design teams did not have to previously face.

Jan. 04, 2010 - Netlist reduction is a vital part of post layout verification flows for all kinds of simulation and analysis. This paper reviews the main categories of applicable algorithms for netlist reduction.

Jan. 04, 2010 - Through years of experience, people develop ‘their’ ways of doing things. With time they become ‘their own’ best engineering practices. Some of these are captured in writing and become part of a Good Engineering Practice (GEP). Some never leave the stage of ‘my’ best engineering practice. ...

Nov. 05, 2009 - We describe the application of stochastic computation to a family of error-correcting decoders. We have applied this technology to the Low Density Parity Check (LDPC) codes first described by Gallagher in the 1960s. LDPC is the highest performance error correcting code known to date and is used in IEEE ...

Oct. 22, 2009 - We need to form a winning team and it's all about performance. We need to find a group of highly skilled people and equip them to perform with peak productivity, predictability, and quality. It would be great to get a few super stars, but we know that it takes both breadth and depth to win. Therefore, ...

Oct. 12, 2010 - Nowadays, the usage of Intellectual Property cores has been an alternative to the increasing gap between design productivity and chip complexity of System-on-chip (SoC) designs [1]. To support this approach, it is mandatory to deliver complete systems in short time-to-market. Thus, IP-core design organizations ...

Oct. 05, 2009 - Some of the most common known issues any equipment manufacturer needs to solve are Time To Market and Time To Volume strong constraints. These issues are also linked with an increased fragmentation of the final products portfolio to be offered, even if often these products are using the same kernel ...

Aug. 03, 2009 - This presentation presents new methodology to improve the SoC verification process. The aim of this methodology is to produce higher quality designs by exposing the hidden corner cases that are not being found. The goal is to move embedded software from execution and inspection to verification.

Jul. 16, 2009 - Applying "dynamic partitioning" to large memory instances eliminates the errors seen in solutions that employ only static Spice netlist-cutting or rely totally on "fast-spice" simulators.

Jul. 13, 2009 - As designers approach 45 nm, the difference between ASICs and SoCs really blurs and, essentially, all chips become SoCs. At the same time, platform-based design, with the use and reuse of internal and external IP blocks, is playing a bigger and bigger role, because nobody is going to build a 50-M gate ...

Jul. 06, 2009 - The design flow of digital signal processing has to be improved. In a specific application, we propose a definition of the IP content and the structure of an IP-based toolbox. The case study consists in an clustering algorithm for spike sorting.

Jul. 06, 2009 - This paper describes the approach adopted by OCP-IP to providing SystemC modelling interfaces for a real memory-mapped bus family. TLM-2.0 has shown itself to be an effective and efficient base technology for all variants of OCP at all levels of abstraction, from cycleaccurate to untimed.

Apr. 20, 2009 - Why not just keep the hash algorithm secret?

Apr. 20, 2009 - To reduce the hassles presented to SoC designers by the DDR2 interface, many problems have been resolved by DDR2 PHY IP development. A DDR2 high speed PHY block is almost always developed as a full custom mixed signal design. There are many good reasons for implementing a full custom design, where every ...

Apr. 13, 2009 - In this paper, we discuss the Transaction Level Model which is being developed to act as Virtual Prototype in digital image processors designed to fit into mobile applications. As part of our developments new methodology TLMdevice is also defined which provides way to connect TLM simulations to communicate ...

Mar. 30, 2009 - On the way to taping out its first PCI Express based SOC, ClearSpeed came face-to-face with the many difficulties of ensuring PCI Express protocol compliance within time and budget constraints. PCI Express is a complex protocol with an extremely large coverage space. From a management perspective, ...

Jan. 26, 2009 - In this paper, Semiconductor Insights shows some noble ways of identifying IP cores from any SoC products to protect the interest of IP core providers. Techniques developed by Semiconductor Insights to identify IP core blocks include methods such as circuit extraction using advanced delayering techniques, ...

Jan. 22, 2009 - Companies should begin to evaluate the ration between competitive and collaborative advantages.

Jan. 19, 2009 - As the semiconductor industry increases take-up of IP-XACT standards to describe Intellectual Property (IP) this paper shares the experiences of NXP Semiconductors and Mentor Graphics, who have been using and developing this technology together for over five years. This paper describes the benefits ...

Dec. 15, 2008 - This paper describes a generalized method to achieve Direct Waveform Synthesis (DWS) for different modulation formats both binary and multi-level, in order to include this mechanism in the general functioning of a software based IP-core. Moreover a generalized approach for designing and managing of ...

Nov. 03, 2008 - With the advent of System-on-Chip technology, designs are becoming bigger in size and thus highly complex, time-to-market is becoming critical, and at the same time, RTL methodologies are generally becoming insufficient to fit into this new role. These factors are driving designers to explore new methodologies ...

Oct. 30, 2008 - FPGA prototyping is not without its difficulties; one major obstacle has been connecting all the logic blocks both within an FPGA and across multiple FPGA devices

Oct. 23, 2008 - Shrinking silicon geometries enable larger SoC-type designs in terms of raw gate size, and many of today's applications take advantage of this trend. An important point that is often missed is the accompanying growth in verification complexity.

Oct. 16, 2008 - In which the author describes how an FPGA with a flexible, soft-core embedded processor fuels a real-time driver drowsiness tracking system.

Sep. 22, 2008 - This paper introduces a unified DFT - PE Methodology, aimed at providing a complete, methodical and fully automated path addressing gaps between DFT and PE team ensuring quick turnaround time in silicon validation.

Aug. 28, 2008 - Using a kit-based approach as part of a complete power-efficient design solution

Aug. 25, 2008 - Designers of consumer product ICs are faced today with the challenges of rapidly increasing complexity, a market with high expectations, and static price points

Aug. 18, 2008 - This paper introduces a visual knowledge-based modelling platform and a system enabling integration of distributed design tools that have been deployed in a distributed collaborative scenario of IP components design

Aug. 07, 2008 - This paper presents de specification, design and implementation of a high performance search engine core. This core implements a regular Associative Memory Array processing in HW and non-structured data management in SW.

Jul. 14, 2008 - This paper briefly discusses the approaches for Validation Environment and Test methodologies adopted for 8-bit microcontroller family based products. The aim of this paper is to raise the awareness for specific advantages/disadvantages, the time saving features and also the amount of reuse facilitated ...

Jul. 08, 2008 - Any viable design methodology requires tight links to implementation, and to meet this need a new generation of High-Level Synthesis tools is emerging, based on SystemC.

Jul. 07, 2008 - The purpose of this paper is to evaluate the benefits of an IP-XACT based environment applied to Network-on-Chip design. We show the level of automation achieved in the design flow, discuss its efficiency for the design and verification steps, and propose improvements.

Jun. 23, 2008 - This paper aims to emphasize on the importance of integrating design for failure analysis in the layout considerations during the IC development process. It will have a brief overview on the importance of failure analysis in an IC development process, followed by an understanding of the failure analysis ...

Jun. 16, 2008 - SystemVerilog for design, power aware design and verification flow, dynamic and formal property verification and transaction level debugging for viewing signals at a higher abstraction level are some of the new techniques getting more attention in the design and verification space.

Jun. 12, 2008 - This paper presents a semi-automatic testbench generation tool called eTBc and a methodology called VeriSC (which allows for testbench simulation before RTL without additional code writing).

Jun. 09, 2008 - Today, complex SOC and ASIC designs require advanced validation and debug solutions that bridge the gap, not just between pre-silicon and post-silicon, but perhaps more importantly, between embedded software and hardware systems.

May. 07, 2009 - This paper discusses the strategies used while verification planning, so that an optimum partition between formal analysis and simulation based functional verification is achieved.

May. 22, 2008 - In this paper, we present a work in progress to provide high level modeling of PDR and a design flow to automatically generate VHDL code from these high level models depending on QoS criteria such as reconfiguration time, performance and power consumption.

May. 22, 2008 - This tutorial describes the different ways in which CPLDs can be used to address the shortcomings associated with handset platforms.