May. 19, 2008 - We present a methodology that allows the rapid creation of application models from bandwidth aware core graphs that are available in the literature for a wide range of applications and we discuss their applicability to the rapid exploration of multiple Networks on Chip (NoCs) layout organizations.

May. 15, 2008 - This paper describes the development of a configurable SoC platform using configurable IP cores, which is designed for low cost, low power and targeted for Bluetooth® and ULP (Ultra Low Power) Bluetooth standalone applications.

May. 12, 2008 - In this case study we attempt to annotate a subset of OVL 2.0 checkers using equivalent SVA properties. In doing so, we define the equivalence between checkers, or assertions, based on what input sequences they can detect as failure sequences

Apr. 28, 2008 - An automated path from concept analysis through design and optimization, to validation and implementation, provides cost effective automotive electronics innovation.

Apr. 21, 2008 - This paper proposes a methodology which addresses the clear needs of the ever-growing SystemC mixedlanguage designs by delivering critical capabilities, including advanced verification features such as; SystemVerilog Assertions (SVA), cover-groups, SystemC Verification (SCV), and more.

Apr. 15, 2008 - Why can't hardware be more like software? It can, even though next generation multicore designs mix programmable logic, CPU blocks, and dedicated logic. But it requires a new approach to architectural design--software-defined silicon.

Apr. 14, 2008 - In an IP-Core based SoC design. A streamlined verification and analysis flow can contribute significantly to the success of a product. A strategy is devised for a more streamlined approach in IP-core based SoC verification which helps in smooth transition from design to chip tape-out stage.

Apr. 11, 2008 - In transitioning from 8 to 32-bit MCU cores, a problem area is how to also improving FLASH memory to match. Here are some efficient methodologies the architect can employ to unclog the performance bottleneck.

Apr. 07, 2008 -

Apr. 02, 2008 - Maximizing verification IP reuse improves verification productivity. The International Technology Roadmap for Semiconductors (ITRS) projects that 75 percent of design/verification productivity improvement will come from IP reuse and 25 percent from improved EDA tools, flow, or methodologies.

Apr. 02, 2008 - Why introduce a new methodology now? With at least three other SystemVerilog methodologies already available, why add another to the mix?

Mar. 24, 2008 - We are at a crossroads in the semiconductor industry, where the difficulty in meeting chip design deadlines is not a lack of proper skills or mature EDA tools, but rather a more insidious demon.

Mar. 20, 2008 - The very process of testing digital circuits routinely increases their dynamic power consumption to levels far exceeding their power specification. If the power consumption is great enough, it can result in failures at wafer probe or pre-burn-in package test that require a significant amount of time ...

Mar. 17, 2008 - ASIC, ASSP and SoC development is, and will always be, a risky and expensive business. Add to this the fact that today functional verification constitutes 50 to 70 percent of the development effort, and it becomes obvious that traditional verification methodologies are no longer by themselves sufficient ...

Mar. 17, 2008 - An IP based development methodology for building system-on-a-chip solution is described. The methodology is illustrated through a memory centric SoC architecture template intended for streaming data applications such as video and audio.

Mar. 10, 2008 - In System on Chip (SoC) architectures, the ability to effectively analyze problems and optimize operations using real time in-system instrumentation is recognized as one of the most effective methods for completing product development.

Feb. 25, 2008 - This paper presents an approach to power design specification intent and associated enabled design methodologies that allow a scalable implementation of voltage islands.

Feb. 14, 2008 - We present an on-line tool for the generation of Configurable IP modules that can be used in Semiconductor devices. This tool allows the generation of customized IP modules, configured according to user requirements which are packaged and delivered to the end-user via the Internet.

Feb. 11, 2008 - To build increasingly sophisticated chips, engineers must be freed from low-level details and limiting methodologies. ESL design flows raise the level of abstraction from the register transfer level (RTL) to the system level.

Feb. 04, 2008 - Increasingly complex systems and technologies like multicore processors and FPGAs have rendered old design methodologies obsolete. New approaches are needed: system-level abstractions that handle complexity, and tools that automate the costly, time-consuming steps between concept and implementation.

Feb. 04, 2008 - The goal of this research is to analyze the mapping between SysML and SystemC, propose and suggest the SystemC modeling techniques that should result in modeling both the structure and behavioral SysML diagram to produce a single executable that represents the system behavior. A prototype for a translation ...

Jan. 28, 2008 - Evolving niche markets, such as ICs for biomedical applications, are very challenging in respect to power consumption and on chip power dissipation, namely, wide range from ultra low power (ULP) functionality (<uW) where IC is battery powered, e.g. mobile micro transducers, to very high power (VHP, ...

Jan. 21, 2008 - This paper presents challenges with the synchronous (clocked) designs and describes the techniques to overcoming the same with asynchronous (Clockless) design methodology. The paper proposes to redesign the synchronous interconnect to an asynchronous interconnect that should cater to tomorrow’s needs ...

Jan. 14, 2008 - This paper describes a new approach for chip design and system-level integration. A hierarchical RTL context-preserving insertion and connectivity methodology has been further implemented in EDA tool – chip IP integrator. This paper shares the approach, methodology and the results on a real-life ...

Jan. 10, 2008 - This paper presents a based on behavioral synthesis design flow that allows high-quality hardware and software design of IP-Cores. The main flow's advantage is that it allows hardware and software to be developed concurrently, reducing design time.

Jan. 07, 2008 - Stan Smith explores challenges and solutions necessary to achieve the closer integration of software development and validation with silicon design and verification.

Jan. 02, 2008 - SoCs are becoming more complex these days. A lot of functionality is being added to chips and data is frequently transferred from one clock domain to another. Hence, clock domain crossing verification has become one of the major verification challenges in deep submicron designs.

Dec. 13, 2007 - Here's how to integrate assembly code into C for maximum performance and programmer productivity. Topics covered include compiler conventions, inlining, intrinsics, register binding, and debugging strategies.

Dec. 10, 2007 - This paper presents a staged scenario generation methodology for SoC verification to control, reuse and scale transaction generation from device level verification to system level verification. This methodology can provide various levels of transaction generation abstraction to reuse, control and scale ...

Oct. 31, 2007 - SoC design isn't getting any easier. Escalating IC densities, rising design complexity and increasingly intricate software interactions are conspiring to reduce predictability and drive up cycle-time risk. At the same time the growing use of software-enabled customizations is quickly rendering existing ...

Oct. 25, 2007 - When designers jump from the 90-nanometer (nm) to 65nm process nodes, many factors conspire to make things more complicated. For instance, at 65nm, designers can fit a lot more functionality onto a chip, which draws considerably more power " unless the designer knows how to optimize for power reduction ...

Oct. 08, 2007 - This whitepaper describes the details of a newly developed processor design within the common ARM Cortex applications profile

Oct. 05, 2007 - The use of Electronic System Level tools, complemented by techniques such as Sequential Logic Equivalence Checking (SLEC), will significantly improve system design productivity especially as designs move to geometries below 90 nanometers.

Sep. 24, 2007 - We present in this paper a model and an implementation of a communication network called mpNoC. This IP permits non-regular communications between PEs in an efficient way. MpNoC is integrated in the mppSoC platform.

Sep. 17, 2007 - Silicon validation " proving the chip works correctly at speed and in system under different operating conditions " is always necessary, even for a "perfect" design. Silicon debug " finding the root cause of a malfunction " is necessary whenever the design turns out to be not entirely flawless.

Aug. 27, 2007 - To create a comprehensive verification solution, we must first acknowledge both the differences and the challenges that designers and verification engineers face. In the process, we find that certain gaps are inadvertently neglected

Aug. 27, 2007 - Designers can verify AMS designs by employing a hierarchical methodology that can directly consume digital and analog blocks in their native modeling languages.

Aug. 09, 2007 - The methodology, tools, and techniques used to address Sun's UltraSPARC T1 system-level verification challenges and deliver a high quality product in a timely manner.

Jul. 30, 2007 - Traditional methods of hardware software co-verification use either the industry standard accelerators/emulators or the instruction set simulators. Both the methodologies are well proven and are well established in SOC verification environment. The design, development and validation of device drivers ...

Jul. 16, 2007 - This paper describes the methodology based on use of functional coverage technology for measurement of quality of IP. In this methodology, the regressions are run on RTL generated by selecting hard configuration parameters randomly. Constraints are defined such that illegal combinations of such parameters ...