Jul. 02, 2007 - This paper explains how individual layered specific verification components such as, Transactor, Checker, Monitor which can be developed using SystemVerilog can be reused when you have all the layers connected at the sub-system and system level, and hence maximizes the verification productivity gains. ...

Jun. 25, 2007 - Smaller process geometries are making it possible to take analog components off the board and incorporate them into the chip together with the digital portions of the designs, increasing the complexity of circuits. Even though there is a rapid increase in today's processor performance, simulation for ...

Jun. 18, 2007 - Although methodologies for power network synthesis typically assume that design tools can freely size sleep transistors for power gating, this assumption does not hold up for real-world SoC designs where the sleep transistors are commonly designed as custom switch cells of fixed sizes.

Apr. 26, 2007 - This paper presents an efficient scalable communication architecture, Data Pre-fetch Core Interface (DPCI), for shared-bus based SOC systems to support scalable and pipelining communication between those IP blocks, the shared memory and the bus so as to improve the system performance and increase the ...

Apr. 19, 2007 - In pursuit of meeting this objective of integrating resources while first silicon success remains the ultimate goal, several approaches are tried and reusability has emerged as a more comprehensive solution. Different teams, different domains and different locations have with them diversified expertise ...

Apr. 12, 2007 - This paper presents a new NOC switch architecture which we have called CTCNOC (Central caching NOC) to offer an attractive way to reduce the system area overhead and increase system performance. The head-of-line and deadlock problems have been significantly alleviated. Through experimentation it has ...

Apr. 10, 2007 - Prototyping an ASIC or SoC design using field programmable gate arrays (FPGAs) can relieve the time bottleneck and remove the high caliber compute resources required to verify the functionality of medium-to-large sized designs. A single FPGA prototype, for example, can serve to verify hardware, firmware, ...

Apr. 05, 2007 - This paper describes a novel approach of remotely diagnosis and testing hardware embedded IP cores within a SoC by using available networking infrastructures between the testing machine and the SoC under test. To this end, classical network management protocols are used to cost-effectively remotely ...

Mar. 26, 2007 - This paper will present in detail practical applications that illustrate the host of issues that hamper the debug of an embedded platform as well as methods to mitigate these problems. We will discuss the debug of a ''Network on Chip'' (NoC) communication mechanism, which while providing potential ...

Mar. 12, 2007 - In this paper it is proposed a systematic platform-based technology, in which a library of reusable IPs (HW and SW) is used together with a set of tools and methodologies to find the optimum solution in this design space, following the IEC61508 guidelines.

Mar. 12, 2007 - In Part 1 in this series, we covered what an asymmetric multi-core application is, and what are the typical problems that can be encountered in such a system. Now that we have an understanding of those issues, we can cover what tools and methodologies available to us to debug systems with these problems. ...

Mar. 12, 2007 - The paper begins with a brief overview of techniques for identification and authentication then follows that with a discussion of technical means to implement them in a System-on-Chip (SoC).

Mar. 05, 2007 - There are many different ways to provide IP protection. This paper will discuss a number of different approaches and the impact each one has on the design environment. There is an industry need to identify a method for the IP provider and the consumer to effectively use the IP in a flow. The objective ...

Feb. 22, 2007 - IP-based SOC designs are increasingly dependent upon ESL methodologies to balance the constantly increasing pressure on both schedule and design complexity. In order to meet these demands, system models need to be generated rapidly and delivered to the teams developing the architecture, coding the ...

Feb. 08, 2007 - This tutorial discusses various issues that must be taken into account when using an FPGA to prototype an ASIC or SoC design.

Jan. 18, 2007 - With FPGA design complexity outpacing CPU speed, FPGA designers are more dependent on design tools and methodologies that speed compile times.

Jan. 08, 2007 - In this article, DDR memory systems will be discussed in the context of consumer electronics design, with an emphasis on the need for a multi-disciplined, system-level approach. A brief look of relevant market pressures are followed by review of key issues in memory system development, including device ...

Jan. 02, 2007 - A fuzzy controller design methodology for the control action in the transport/diffusion is presented here. The efficient design of the controller according to the desired specifications using VHDL and its implementation on FPGA introduces a novel approach for realizing a generic prototype of the controller, ...

Dec. 14, 2006 - Nokia utilizes the Open Core Protocol (OCP) as a standard interconnection architecture for its systems. So far there has not been a unified verification methodology for interconnections available.

Dec. 11, 2006 - When designing a System-On-Chip (SoC) for safetycritical or high-reliability applications, the design space that a system architect must consider is rather large due to the variety of faults that can affect the SoC, the different failures that these faults can generate and the wide set of techniques ...

Dec. 04, 2006 - Hardware and embedded software development at the system-level will only require more verification cycles and proven methodologies to adhere to the specification to expose system-level errors and manage overall project risk

Nov. 23, 2006 - To close the gaps in systems development across distributed design and verification teams it will become necessary to plan, design, and verify embedded software closer in-line with the way we currently design and verify hardware.

Nov. 17, 2006 - The hardware design techniques employed for an application will establish the baseline immunity performance. The purpose of hardware techniques is to reduce the level or frequency content of immunity signals below that needed to cause performance degradation or long-term microcontroller (MCU) reliability ...

Nov. 02, 2006 - Self-timed packet-switched networks are poised to take a major role in addressing the complex system design and timing closure problems of future complex Systems-on-Chip.

Oct. 30, 2006 -

Sep. 05, 2006 - Using complete, integrated DDR2 SDRAM memory physical interface IP solutions can significantly reduce the risks associated with combining discrete memory subsystem blocks, such as interoperability and schedule. Packaged as a complete, integrated place-and

Aug. 17, 2006 - To help the embedded industry accelerate the adoption of multi-core devices, several key ingredients must be developed, including open standards to enable vendors’ products to work together, and another is the availability of standard benchmarks.

Aug. 14, 2006 - This paper discusses the integration and system verification challenges encountered when integrating a PCI Express digital intellectual property (IP) core into a Gigabit Ethernet design

Aug. 10, 2006 - Recent advances in C-to-FPGA design methodologies and tools facilitate the rapid creation of hardware-accelerated embedded systems.

Jul. 17, 2006 - This article presents an elegant methodology using pulsed latch instead of flip-flop without altering the existing design style. It reduces the dynamic power of the clock network, which can consume half of a chip's dynamic power. Real designs have shown a

Jul. 06, 2006 - Using a Flash MCU based on the industrystandard ARM processor as a platform represents a practical approach to SoC development that addresses all these issues.

Jun. 27, 2006 - Designers might hesitate to use ESL because of legacy RTL intellectual-property libraries that represent thousands of man-years of invested time. But legacy RTL IP can be the basis for new designs that leverage ESL methodologies.

Jun. 19, 2006 - In this paper, we examine the need for formal sequential equivalence checking across pairs of RTL models.

Jun. 12, 2006 - Increasing complexity and shrinking schedules push designers to use new methodologies

Jun. 12, 2006 - An efficient method of Packaging Silicon IP and then testing /synthesizing it for multiple configurations has been described

May. 25, 2006 - We propose in this article a methodology based on measurements allowing to model the application power consumption on FPGA with architectural and algorithmic parameters.

May. 22, 2006 - This paper describes a transaction based framework for reusing tests and modeling based on inter-language function calls (ILFC) using SystemVerilog DPI (Direct Programming Interface) [1] and C

May. 18, 2006 - The paper deals with the power optimisation techniques which can be applied to any design core which is selected to be used in a ASSP design. Bluetooth base band core was considered for power study. It is shown that power saving to the tune of around 20%

May. 11, 2006 - How Silicon IP Will Change the Semiconductor Supply Chain

May. 08, 2006 - In this paper, we present a NoC-based communication framework that is used to develop complex chips including a large number of heterogeneous IPs