May. 01, 2006 - This paper will describe the best use of software and hardware tools combined with verification IP in a multi-layered verification methodology as applied to real designs – in this case targeted at PCI Express applications.

May. 01, 2006 - This paper describes an innovative methodology that makes use of XML-based IP descriptions, including constraints information, to produce automatically synthesis, STA and formal verification tool scripts for sub-systems. The XML information can be conside

Apr. 27, 2006 - To some degree, FPGA prototyping has become commonplace in the majority of SoC development programs. This paper is a brief discussion of four aspects of this type of approach.

Apr. 24, 2006 - The paper goes on to describe the opportunities presented by platform-centric scheduling in terms of dynamically managing performance and power efficiency at runtime. Having established the benefits of such an abstraction the runtime performance is then

Apr. 20, 2006 - IP selection, verification and integration are key aspects to the success of an IP-based design. This paper describes some of the challenges imposed by an IP based implementation of the technology and discusses about possible solutions to address them.

Apr. 13, 2006 - This paper will explain how new ASSP ventures face challenges that can derail success of a product even before the first device is sold, including market entry barriers such as time to market pressures, limited human and financial resources, and increased

Apr. 11, 2006 - This tutorial explains how Platform FPGAs can be used to meet the challenges of today's demanding high-performance real-time DSP applications

Mar. 30, 2006 - Verification is one of the most critical and challenging tasks, which takes almost 50 % of the complete design and verification cycle. With the complexity of the designs on the rise and with that also the verification effort, new challenges are to reduce

Mar. 23, 2006 - In this paper the reasons why the gap exists and some practical approaches on how to fill the gap are explored. With this understanding, the different IP cost structures of license fee and royalties are discussed to see which fits best in which situation

Mar. 09, 2006 - This paper will look at a typical application of transactions for embedded processor platform modeling and debug across a PCI Express based system. It will examine how transactions are leveraged to improve the performance, verification, and simulation eff

Mar. 06, 2006 - In this paper, we introduce a methodology for protection of HDL Intellectual Property, which enables platform independent protection, seamless integration of IP in all kinds of HDL designs, compatibility of the solution across the verification flow and mu

Mar. 02, 2006 - This paper discusses power estimation at the system level. It shows why power estimation at the pre-RTL level is important and how it can be meaningfully applied during system level design. Special attention will be given to the role of dynamic data durin

Feb. 20, 2006 - This paper will introduce a unified DFT Verification Methodology, aimed at providing a complete, methodical and fully automated path from test specification to DFT closure. We will also examine the benefits of this approach, looking at how this methodolog

Feb. 16, 2006 - The DesignWare® IP solution for the AMBA 3 AXI protocol enables designers to quickly and easily integrate the high-speed protocol into their (SoC) designs, while reducing risk and speeding time to results

Feb. 06, 2006 - The verification examples used in this article are based on the following 0.18um designs - ARC based digitizer for notebook PCs, MIPS based wireless multimedia processor for HDTV and ARM based vision processor for automotive applications

Jan. 30, 2006 - Just as floorplanning has become vital to the success of system-on-chip (SoC) design, package-aware I/O planning is essential for meeting cost, time-to-market and performance targets

Jan. 30, 2006 - This paper briefly surveys ESL and IP-based design, outlines the requirements for supporting design with multiple configurable, extensible processors, and sketches the characteristics of possible solutions

Jan. 19, 2006 - This paper will explain how new ASSP ventures face challenges that can derail success of a product even before the first device is sold, including market entry barriers such as time to market pressures, limited human and financial resources, and increased

Jan. 05, 2006 - This paper discusses a new, inexpensive verification approach that enables teams to reduce the time to find a bug in the lab through greater reuse of tests between the simulation and lab environments.

Jan. 05, 2006 - The demand to deliver faster, smaller, portable and more powerful wireless products is what drives the electronics market

Jan. 03, 2006 - In this paper, we present a NoC-based communication framework that is used to develop complex chips including a large number of heterogeneous IPs

Oct. 13, 2005 - This article discusses the road to achieving compliance and the role that Synopsys DesignWare Intellectual Property (IP) for PCI Express can play in helping to achieve interoperability and compliance

Sep. 22, 2005 - by Eric Cigan, AccelChip Inc. & Ir. Aaik van der Poel, Synopsys

Sep. 19, 2005 - To understand why scan technology remained in the background of IC test for so many years — and to appreciate its recent advances — you need to peek under the radar screen and examine its genesis, evolution, and possible future

Sep. 06, 2005 - This brief article will discuss how to plan DfT verification against test intent, ensure compatibility with standards and functional correctness, and create a complete, methodical and fully automated path from specification to closure

Aug. 29, 2005 - The X Architecture represents the pervasive use of both Manhattan and diagonal interconnect on a chip.

Aug. 22, 2005 - by Brian Bailey

Aug. 10, 2005 - End applications continue to demand increased flexibility, configurability and performance, along with reduced power demands, board space and cost

Aug. 15, 2005 - First it was single ended drivers, then differential pairs, and now adaptive drivers and receivers are used to coax data down copper interconnects as fast as possible

Aug. 08, 2005 - Writing individual tests is impractical for today’s large, complex designs because the state space and number of test conditions is simply too large to code by hand, leading to insufficient test coverage

Jul. 25, 2005 - Electronic system-level (ESL) design is a set of methodologies that enables SoC engineers to efficiently develop, optimize and verify complex system architectures and embedded software

Jul. 25, 2005 - The network-on-Chip (NoC) design paradigm is viewed as an enabling solution for the integration of an exceedingly high number of computational and storage blocks in a single chip

Jul. 13, 2005 - As feature sizes continue to shrink at a breakneck pace, transistor-level analysis and optimization in digital design is becoming a necessity for achieving a solution with the unique combination of performance, power, and area

Jun. 20, 2005 - An analog and mixed-signal IP company needs to excel using its creative resources, so it must leverage core skills to produce a growing product portfolio. But with customer evaluations becoming increasingly complex, it is just as necessary to leverage sca

Jun. 12, 2005 - By Bassam Tabbara, Novas Software, Inc., USA and Kamal Hashmi, SpiraTech, Ltd., UK

Jun. 06, 2005 - Mixed-signal verification lies at the heart of a designer's constant battle between silicon accuracy and shorter development time.

Jun. 06, 2005 - Electronic system-level development: Finding the right mix of solutions for the right mix of engineers

May. 05, 2005 - by Riccardo Mariani, Natale Barsotti - YogiTech SpA

May. 05, 2005 - by Mick Posner, Darrin Mossor from Synopsys

Apr. 25, 2005 - Using the right methodology for applying and using products within a design project is critical to getting a high return on investment (ROI). This is especially true in emerging areas such as formal analysis.