| MONTEREY, Calif. — Design automation needs to provide an integrated approach to system-level design, said John Darringer, manager for system-level design at IBM's T.J. Watson research center, in a keynote speech at the Electronic Design Processes (EDP) workshop here Thursday (April 7). Darringer also called for merging the "best" of the ASIC and processor design methodologies, and outlined a design approach for future "servers on a chip" that IBM intends to build. Darringer showed how business trends are placing pressure on systems designers to increase parallelism, exploit low-latency communications, accelerate tasks, build scalable systems, and reduce cost of ownership. System design is becoming more complex and is demanding an analysis of tradeoffs, workloads, and new software architectures, he said. "If you look at the tools experts use, they're typically spreadsheets," he said. "Then they team up with people who build some custom models." These include technology models for energy, power, timing, and yield, along with performance models for cores, caches, busses, I/Os, and memories. The trouble is that these models are written by different individuals, and they have no connection to one another. Then there is, at best, a "vague handoff" to RTL design, based on various documents. "Power, performance, and interconnect models all have unique representations. They don't even have compatible inputs and outputs. We've got to fix that. I need a way to bring these models together," Darringer said. The need is especially great, Darringer said, because of the growing complexity of tradeoffs with the advent of multiple threshold voltages, clock and power gating, voltage islands, asynchronous design, and other new techniques. One approach that's gained some attention is "globally asynchronous, locally synchronous" (GALS) design. But GALS design raises a number of questions, Darringer noted. How many partitions, what's the best place to partition, what's the synchronization penalty? "If you look at the traditional models within IBM to do this, you could modify them forever," he said. "I need a way to do this quickly." "I'm not saying we need new performance modeling techniques," he said. "We have good techniques. But the frustrating thing is that the work is not connected to work done by other teams." In addition to a more integrated modeling approach, a direct transfer to RTL is needed, Darringer said. He suggested this could be facilitated by extending the OpenAccess database to architectural design. Darringer also spoke of the need for modeling at intermediate levels, with formal verification used between the levels. Darringer also noted growing similarities between ASIC and processor design. "In my view the server guys are heading to the same place as the processor guys," he said. "Both have more cores, I/O, memory, and accelerators. A common bus structure will probably emerge that brings these guys together." Future servers-on-a-chip, he said, will involve system-level assembly, "efficient" custom design, synthesis of non-custom components, accurate planning for power and timing, and automatic chip integration. One thing that's common to both IBM ASIC and processor design, Darringer noted after the keynote, is a reliance on internal tools. "We're always trying to figure out how to take advantage of vendor tools, but IBM is very strong on developing internal tools," he noted. EDP, now in its twelfth year, is a two-day IEEE-sponsored workshop focusing on electronic design methodologies. | 
