Mentor Graphics Configurable Port is Compliant with the PCI Express Specification

WILSONVILLE, Ore.--(BUSINESS WIRE) -- April 13, 2005 -- Mentor Graphics Corporation (Nasdaq:MENT), a leader in standards-based semiconductor intellectual property (IP), today announced that its MPCIExp(TM) Configurable Port is compliant with the PCI Express specification from the PCI-SIG. The company has demonstrated that the Configurable Port works successfully with Rambus' Physical Layer (PHY) IP.

Mentor Graphics(R) IP core, based on the PCI Express architecture, is fully compliant with the PCI Express standard, providing the highest quality IP that minimizes development risk and lowers overall system costs. As a result, design engineers can focus on the differentiating aspects of their design and accelerate design time with highly configurable, reusable, low-cost IP building blocks to create innovative electronic systems.

The PCI-SIG used an established set of compliance tests during the organization's Compliance Workshop the week of February 21, 2004 in Milpitas, California. Products must pass these tests to be included in the PCI-SIG Integrators List. This list offers the latest data on PCI device testing from member companies to help users maximize interoperability with a variety of platforms and form factors, and adhere to current industry standards. The list is available at: www.pcisig.com/developers/compliance_program/integrators_list/pcie/

"Mentor has demonstrated the value of the PCI-SIG compliance program by successfully testing the interoperability of its MPCIExp-CP IP product," stated Tony Pierce, PCI-SIG chairman. "Compliance will enable Mentor's customers to quickly implement the development of their systems based on the PCI Express specification."

"The collaboration with Mentor Graphics as a key IP partner helps realize the value of the PCI Express standard by enabling our customers to deliver innovative products with more confidence," stated Jean-Marc Patenaude, director of marketing at Rambus. "Mentor's leading digital controllers and configurable port combined with Rambus's PHY IP provide a full range of proven PCI Express solutions."

The Rambus RaSer PHY is based on the PCI Express specification and is silicon-proven on multiple foundry and captive processes at every process node ranging from 180nm to 65nm. Rambus customers are shipping graphics, chipset, switch and bridge chips for applications using the PCI Express standard. Rambus has also demonstrated its Turbo platform based on the PCI Express specification with serial links operating at 5- 6.4Gbps data rates to meet future PCI Express requirements.

"Rambus has the broadest portfolio of PHY products based on the PCI Express specification and was the first to deliver silicon-proven PHYs," stated Dave Wood, PCI Express product marketing manager at Mentor Graphics. "This strategic partnership and our compliance ensure confidence that our PCI Express solution minimizes risk and accelerates the development of new and emerging products exploiting this new standard."

For more information on the PCI-SIG, please visit www.pcisig.com.

Mentor Graphics IP Solution for PCI Express

Mentor's synthesizable core implements the PCI Express specifications in a highly configurable block that provides transaction layer, data link layer, and Media Access Controller (MAC) functionality down to the PHY interface for the PCI Express PIPE(TM) interface. For added flexibility, the core can implement L1 and L2 features of the ASI specification and there is an option of operation either as a root or as an endpoint with the choice made at boot time.

The Mentor Graphics IP core for PCI Express implements a rich set of features in hardware including End-to-End Cyclic Redundancy Check (ECRC), Advanced Error Reporting (AER), hot plugging, power management, crosslink, lane reversal, Message Signal Interrupt (MSI) and cut-through. Engineers are able to vary the number of lanes, virtual channels, and traffic classes. The core offers configurable buffer resources for each channel and Data Link Layer (DLL) retry.

Additional features include:

• Scalable architecture: x1, x2, x4, x8 lanes at 2.5 Gbps
• Up to 4,096 byte packets for Tx and Rx and retry buffers
• 64- FIFO-based back-end interface
• 8- or 16-bit PIPE interface to SerDes PHY
• Configurable Port for PCI Express specification is available in Verilog source code with a high-level functional testbench and documentation
• Complementary to Mentor Graphics verification products such as the iSolve(TM) speed adapter and the ModelSim(R) verification environment for the PCI Express specification
• Interoperable with the Rambus RaSer PHY

Mentor Graphics Silicon-Proven, Standards-based Intellectual Property

Mentor Graphics offers a variety of industry-leading, standards-based IP cores that are rigorously tested and validated to provide design teams with the most reliable cores in the industry. Mentor Graphics IP portfolio ranges from simple SoC building blocks, such as communications interfaces and microcontrollers, to an expansive offering of products for Ethernet, USB, Storage and PCI Express applications. To find out more about Mentor's intellectual product offerings, visit www.mentor.com/products/ip/.

About Mentor Graphics

Mentor Graphics Corporation (Nasdaq:MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $700 million and employs approximately 3,850 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: www.mentor.com.

Mentor Graphics is a registered trademark and MPCIExp is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.