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Faraday Verifies Complex CPU Cores with Synopsys' VCS and Vera Verification Solutions
Advanced Coverage and Testbench Technologies in the Synopsys Discovery™ Verification Platform Enable Robust Validation of Faraday's Processor IP
MOUNTAIN VIEW, Calif. and HSINCHU, Taiwan, May 10, 2005 -- Synopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, and Faraday Technology Corporation (TAIEX: 3035), a leading fabless ASIC and IP provider, today announced that Faraday has successfully used Synopsys' VCS® comprehensive RTL verification solution and Vera® testbench automation tool to optimize the verification process for Faraday's FA series of complex 32-bit RISC processor cores. Synopsys' industry-leading verification solutions enabled Faraday's verification team to complete verification with a high quality of results and a high degree of confidence. "We are committed to providing our SoC customers with high-quality processor cores and the means to achieve design success," said Thomas Hsieh, associated vice president of R & D at Faraday. "In our endeavor to deploy the best verification solution for our CPU cores, we used the native coverage features in Synopsys' VCS RTL verification solution to quickly and easily check the completeness of our RTL verification. We also used the Vera tool to create a comprehensive verification environment to allow us to ensure that the functional coverage goals were met as specified." The combination of Synopsys technology and Faraday methodology enables a solution that yields high-quality Faraday CPU cores. With the use of Synopsys' VCS and Vera verification solutions and Faraday's constrained-random test methodology, working silicon-proven processor IP was quickly produced. By using the Vera tool to generate testbenches with constrained-random patterns and functional coverage, the Faraday verification team reached its functional coverage goals very quickly. At the same time, the VCS solution's built-in coverage metrics enabled the team to measure the completeness of its RTL code coverage during simulation. "Ensuring design robustness is critical for all development teams," said Farhad Hayat, vice president of Marketing, Verification Group, Synopsys, Inc. "Design and verification engineers need effective ways to measure verification progress and rapidly meet their coverage goals. Synopsys' advanced testbench technologies, now available natively in the VCS solution for even higher performance, help our customers achieve high quality on very tight schedules." Synopsys Discovery Verification Platform About Synopsys About Faraday Technology Corporation DesignWare, OpenVera, VCS and Vera are registered trademarks of Synopsys, Inc. Discovery is a trademark of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
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