Denali Announces Dataplex IP Product for DDR, Flash, and SATA Subsystems

Integrated Data-Subsystem IP Leverages Databahn Technology, Addresses Quality, Performance, and Speed of Deployment

PALO ALTO, Calif., May 23 /PRNewswire/ -- Denali Software, Inc., the leading provider of electronic design automation (EDA) tools and intellectual property (IP) solutions for chip interface design and verification, today announced Dataplex(TM), a new data-subsystem IP product for DRAM, Flash and hard disk drive interfaces.

With this announcement, Denali gives chip designers access to a single IP solution that controls off-chip storage devices and optimizes the dataflow from these devices to the system on chip (SoC).

Dataplex provides application-specific configurability, state-of-the-art features, and proven performance in one integrated IP subsystem. It supports a variety of SoC bus interfaces and provides multi-port arbitration for optimal system-level data access. Dataplex also leverages Denali's Databahn(TM) IP technology to provide component-level configurability, effectively insulating SoC designers from fast-changing protocols and details associated with interfaces such as SATA, Flash and DDR memory.

"Our customers view this data-subsystem IP as a critical piece of the SoC design puzzle," says Brian Gardner, Denali's director of IP Product Marketing. "They can get IP for processors, DSPs and embedded memory. Until now, no one has been able to provide a configurable, high-quality solution that bridges the gap between off-chip data storage and the needs of the system design as a whole. By integrating the control of these various storage interfaces, we're able to offer value in data flow optimization, design quality, configurability and overall cost of ownership."

Dataplex leverages Denali's proven Databahn IP technology used in more than 150 designs, including 47 designs in silicon. More than a collection of standalone IP components, Dataplex incorporates a number of new system elements, including an advanced Direct Memory Access (DMA) engine that optimizes movement of data to and from DRAM, reduces CPU overhead, and allows for better firmware portability.

Configured for mobile applications, Dataplex supports Mobile DDR memory and NAND Flash devices with an optimized DMA and built-in configurability for a wide range of power and performance requirements. A unique hardware abstraction layer allows for easy Flash driver migration across many different types of Flash memory.

Dataplex provides an integrated IP solution for off-chip memory and storage, and is supported by a robust configuration and verification environment that enables system designers to achieve maximum performance with minimum risk. Deliverables include: register transfer level (RTL) and synthesis scripts, silicon-independent DDR PHY, verification testbench, static timing analysis (STA) scripts, documentation, and programmable register settings for power management, port arbitration, DMA, and device settings. Dataplex is library independent and supports from .18-micron to .09-micron technologies. Features include:

• Proven DRAM Controller Core -- Dataplex leverages Denali's multi-port Databahn DRAM controller that features an advanced, pipelined architecture to ensure optimal utilization of available bandwidth for SDRAM, DDR1, DDR2, and Mobile DRAM devices.
• Support for New and Emerging Memory and Storage Devices -- Dataplex supports the following device types alone or in combination: SDRAM, DDR1-SDRAM, DDR2-SDRAM, Mobile SDRAM, Mobile DDR-SDRAM, NAND Flash, OneNAND Flash, NOR Flash, Serial ATA (1.5Gbps and 3Gbps).
• Advanced Multi-port Arbitration -- Dataplex supports multiple SoC ports of varied width and types, including AXI, OCP, AHB, BVCI, PLB, and a thin, native protocol. Programmable bandwidth-based priority algorithms ensure quality of service, and a sophisticated ordering engine reorders commands to optimize bandwidth utilization while maintaining data coherency.
• Integrated DMA Engines -- Tight integration of SATA and Flash controllers with the DRAM controller enables Dataplex IP to minimize CPU activity and unnecessary data transfers through the system bus. Each controller includes a DMA engine with an interface designed to simplify driver firmware and allow drivers to be more portable among device vendors and product generations.
• Simplified Firmware Development -- Dataplex utilizes simpler, standards-based interfaces to reduce firmware development time and increase firmware portability. The SATA DMA conforms to an existing SATA HBA specification. The Flash controller includes a hardware abstraction layer for generic driver development.

Dataplex will be demonstrated at the 42nd Design Automation Conference (DAC) in Denali's Booth Number 1073 from June 13-16 at the Anaheim Convention Center in Anaheim, Calif.

For more complete information about Dataplex, contact sales@denali.com, or visit Denali online at: http://www.denali.com

About Denali

Denali Software Inc. is the world's leading provider of EDA tools and Intellectual Property (IP) solutions for chip interface design, integration and verification. Its Databahn(TM) Design IP products offer fully configurable design cores for complex interfaces such as Serial ATA II and DDR-based memory systems. Denali's PureSpec(TM) Verification IP product supports all complex interfaces, including PCI Express, Advanced Switching Interconnect (ASI), USB, Ethernet and Serial ATA. More than 400 companies worldwide use Denali's tools, technology, and services to design and verify complex chip interfaces for communication, consumer, and computer products. For more information, visit Denali at http://www.denali.com. Telephone: (650) 461-7200. 

The Denali logo, Denali, Dataplex, Databahn, PureSpec, and MMAV are trademarks of Denali Software Inc. PCI Express is a registered trademark of PCI-SIG. All other trademarks are the property of their respective owners.